參數(shù)資料
型號： AD9991KCP
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC56
封裝： 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁數(shù)： 2/60頁
文件大?。?/td> 826K
代理商： AD9991KCP
AD9991
–2–
TABLE OF CONTENTS
SPECIFICATIONS ...............................................................3
Digital Specifications ..........................................................3
Analog Specifications...........................................................4
Timing Specifications...........................................................5
ABSOLUTE MAXIMUM RATINGS.....................................5
PACKAGE THERMAL CHARACTERISTICS ......................5
ORDERING GUIDE .............................................................5
PIN CONFIGURATION .......................................................6
PIN FUNCTION DESCRIPTIONS.......................................6
TERMINOLOGY ..................................................................7
EQUIVALENT CIRCUITS....................................................7
TYPICAL PERFORMANCE CHARACTERISTICS .............8
SYSTEM OVERVIEW............................................................9
PRECISION TIMING HIGH SPEED TIMING
GENERATION....................................................................10
Timing Resolution .............................................................10
High Speed Clock Programmability....................................10
H-Driver and RG Outputs.................................................11
Digital Data Outputs ........................................................11
HORIZONTAL CLAMPING AND BLANKING.................13
Individual CLPOB and PBLK Patterns ..............................13
Individual HBLK Patterns .................................................13
Generating Special HBLK Patterns....................................14
Generating HBLK Line Alteration .....................................14
HORIZONTAL TIMING SEQUENCE EXAMPLE .............15
VERTICAL TIMING GENERATION .................................16
Vertical Pattern Groups......................................................17
Vertical Sequences..............................................................18
Complete Field: Combining V-Sequences ...........................19
Generating Line Alternation for V-Sequence and HBLK......20
Second V-Pattern Group during VSG Active Line................20
Sweep Mode Operation......................................................21
Multiplier Mode................................................................21
Vertical Sensor Gate (Shift Gate) Patterns...........................22
MODE Register ................................................................23
VERTICAL TIMING EXAMPLE ....................................... 24
Important Note about Signal Polarities...............................24
SHUTTER TIMING CONTROL ........................................26
Normal Shutter Operation .................................................26
High Precision Shutter Operation.......................................26
Low Speed Shutter Operation ............................................26
SUBCK Suppression.........................................................27
Readout after Exposure......................................................27
Using the TRIGGER Register............................................27
VSUB Control...................................................................28
MSHUT and STROBE Control ........................................28
TRIGGER Register Limitations .........................................29
EXPOSURE AND READOUT EXAMPLE..........................30
ANALOG FRONT END DESCRIPTION
AND OPERATION ......................................................... 31
DC Restore ..................................................................... 31
Correlated Double Sampler............................................... 31
Variable Gain Amplifier .................................................... 31
A/D Converter ..................................................................31
Optical Black Clamp......................................................... 3
2
Digital Data Outputs .........................................................32
POWER-UP AND SYNCHRONIZATION...........................33
Recommended Power-Up Sequence for Master Mode.........33
Generating Software SYNC without
External SYNC Signal ...................................................33
SYNC during Master Mode Operation...............................3
4
Power-Up and Synchronization in Slave Mode....................34
STANDBY MODE OPERATION ........................................34
CIRCUIT LAYOUT INFORMATION.................................36
SERIAL INTERFACE TIMING...........................................37
Register Address Banks 1 and 2..........................................38
Updating of New Register Values........................................39
COMPLETE LISTING OF REGISTER BANK 1............... 40
COMPLETE LISTING OF REGISTER BANK 2............... 43
OUTLINE DIMENSIONS.................................................. 59
REV. 0
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