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參數(shù)資料
| 型號： | AD9991KCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 32/60頁 |
| 文件大?。?/td> | 826K |
| 代理商： | AD9991KCP |
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AD9991
–32–
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel inter-
val on each line, the ADC output is compared with a fixed black
level reference, selected by the user in the Clamp Level register.
The value can be programmed between 0 LSB and 63.75 LSB in
256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamp-
ing is used during the postprocessing, the AD9991 optical black
clamping may be disabled using Bit D2 in the OPRMODE regis-
ter. When the loop is disabled, the Clamp Level register may still
be used to provide programmable offset adjustment.
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter pulse-
widths may be used, but clamp noise may increase, and the ability
to track low frequency variations in the black level will be reduced.
See the Horizontal Clamping and Blanking section and the Hori-
zontal Timing Sequence Example section for timing examples.
Digital Data Outputs
The AD9991 digital output data is latched using the DOUT
PHASE register value, as shown in Figure 33. Output data timing
is shown in Figure 8. It is also possible to leave the output latches
transparent so that the data outputs are valid immediately from
the A/D converter. Programming the AFE CONTROL register bit
D4 to a 1 will set the output latches transparent. The data outputs
can also be disabled (three-stated) by setting the AFE CONTROL
register bit D3 to a 1.
The data output coding is normally straight binary, but the coding
my be changed to gray coding by setting the AFE CONTROL
register Bit D5 to 1.
REV. 0
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9991KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 56-Pin LFCSP EP T/R |
| AD9991KCPZ | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9991KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9992 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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