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參數(shù)資料
| 型號： | AD9991KCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 826K |
| 代理商： | AD9991KCP |
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AD9991
–17–
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each V1–V6 output signal. Table V summarizes the registers
available for generating each of the 10 V-pattern groups. The start
polarity (VPOL) determines the starting polarity of the verti-
cal sequence, and can be programmed high or low for
each V1–V6 output. The first, second, and third toggle posi-
tion (VTOG1, VTOG2, VTOG3) are the pixel locations within
the line where the pulse transitions. A fourth toggle position
(VTOG4) is also available for V-Pattern Groups 8 and 9. All tog-
gle positions are 12-bit values, allowing their placement anywhere
in the horizontal line. A separate register, VPATSTART, specifies
the start position of the V-pattern group within the line (see the
Vertical Sequences section). The VPATLEN register designates
the total length of the V-pattern group, which will determine the
number of pixels between each of the pattern repetitions, when
repetitions are used (see the Vertical Sequences section).
The FREEZE and RESUME registers are used to temporarily
stop the operation of the V1–V6 outputs. At the pixel location
specified in the FREEZE register, the V1–V6 outputs will be
held static at their current dc state, high or low. The V1–V6
outputs are held until the pixel location specified by RESUME
register. Two sets of FREEZE/RESUME registers are pro-
vided, allowing the vertical outputs to be interrupted twice in
the same line. The FREEZE and RESUME positions are pro-
grammed in the V-pattern group registers, but are separately
enabled using the VMASK registers, which are described in the
Vertical Sequence section.
Table V. Vertical Pattern Group Registers
Register Length Range Description
VPOL 1b High/Low Starting Polarity of Each V1–V6 Output
VTOG1 12b 0–4096 Pixel Location First Toggle Position within Line for Each V1–V6 Output
VTOG2 12b 0–4096 Pixel Location Second Toggle Position within Line for Each V1–V6 Output
VTOG3 12b 0–4096 Pixel Location Third Toggle Position within Line for Each V1–V6 Output
VTOG4 12b 0–4096 Pixel Location Fourth Toggle Position, only Available in V-Pattern Groups 8 and 9
VPATLEN 12b 0–4096 Pixels Total Length of Each V-Pattern Group
FREEZE1 12b 0–4096 Pixel Location Holds the V1–V6 Outputs at Their Current Levels (Static DC)
RESUME1 12b 0–4096 Pixel Location Resumes Operation of the V1–V6 Outputs to Finish Their Pattern
FREEZE2 12b 0–4096 Pixel Location Holds the V1–V6 Outputs at Their Current Levels (Static DC)
RESUME2 12b 0–4096 Pixel Location Resumes Operation of the V1–V6 Outputs to Finish Their Pattern
HD
V1
PROGRAMMABLE SETTINGS FOR EACH V-PATTERN:
1. START POLARITY
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION (THIRD TOGGLE POSITION ALSO AVAILABLE, FOURTH TOGGLE POSITION AVAILABLE FOR V-PATTERN GROUPS 8 AND 9)
4. TOTAL PATTERN LENGTH FOR ALL V1–V6 OUTPUTS
START POSITION OF V-PATTERN GROUP IS PROGRAMMABLE IN V-SEQUENCE REGISTERS
4
1
2
3
V2
1
2
3
V6
1
2
3
Figure 16. Vertical Pattern Group Programmability
REV. 0
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