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參數(shù)資料
| 型號(hào)： | AD9260AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | MS-022AB, MQFP-44 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大小： | 572K |
| 代理商： | AD9260AS |
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AD9260
–31–
REV. B
For two-tone input signals
: The user would leave jumpers (JP8)
connected and use IN-1 and IN-2 (J7 and J6) as the connec-
tors for the input signals.
For signal tone input signal
: The user would remove jumper
(JP8) and use only IN-1 as the input signal connector.
Selectable Input Signal Common-Mode Level Source:
The input signal
’
s common-mode level (CML) can be set by
U10.
To use the Input CML generated by U10
: Disconnect jumper
JP13 and Connect resistors RX3 and RX4. The CML gener-
ated by U10 is variable and adjustable using the 1 k
trimpot R35.
SHIPMENT CONFIGURATION AND QUICK SETUP
The AD9260 Evaluation Board is configured as follows when
shipped:
1. 2.5 V external reference/4.0 V differential full-scale input:
JP5, JP9 and JP10 connected, JP6 and JP7 disconnected.
2. 8
×
Mode/OSR: JP1 connected, JP2, JP3, and JP4
disconnected
.
3. Full Speed Power Bias: R2 = 2 k
and connected.
4. CSB pulled low: R6 = 49.9
and connected, R29
disconnected.
5. RESETB pulled high: R7 = 10 k
and connected, R30 dis-
connected.
6. READ pulled high: R28 = 10 k
and connected, R5
disconnected
.
7. Single Tone Input: JP8 removed, input applied via IN-1 (J7).
8. Input signal common-mode level set by Trimpot R35 to
2.0 V: Jumper JP12 is disconnected and resistors Rx4 and
Rx3 are connected.
9. AC Coupled Clock: JP12 connected and JP11 disconnected.
Note: 50
terminated by R27.
QUICK SETUP
1. Connect the required power supplies to the Evaluation
Board as illustrated in Figure 22:
±
5 VA supplies to P5
—
Analog Power
+5 VA supply to P4
—
Analog Power
+5 VD supply to P3
—
Digital Power
+5 VD supply to P2
—
Driver Power
2. Connect a Clock Source to CLKIN (J1): Note: 50
termi-
nated by R1.
3. Connect an Input Signal Source to the IN-1 (J7).
4. Turn On Power!
5. The AD9260 Evaluation Board is now ready for use
.
APPLICATION TIPS
1. The ADC analog input should not be overdriven. Using a
signal amplitude slightly lower than FSR will allow a
small amount of
“
headroom
”
so that noise or DC offset
voltage will not overrange the ADC and
“
hard limit
”
on
signal peaks.
2. Two-tone tests can produce signal envelopes that exceed
FSR. Set each test signal to slightly less than
–
6 dB to pre-
vent
“
hard limiting
”
on peaks.
3. Bandpass filtering of test signal generators is absolutely
necessary for SNR, THD and IMD tests. Note, a low noise
signal generator along with a high Q bandpass filter is often
necessary to achieve the attainable noise performance of the
AD9260.
4. Test signal generators must have exceptional noise perfor-
mance to achieve accurate SNR measurements. Good gen-
erators, together with fifth-order elliptical bandpass filters,
are recommended for SNR tests. Narrow bandwidth crystal
filters can also be used to filter generator broadband noise,
but they should be carefully tested for operation at high-
signal levels.
5. The analog inputs of the AD9260 should be terminated
directly at the input pin sockets with the correct filter termi-
nating impedance (50
or 75
), or it should be driven by
a low output impedance buffer. Short leads are necessary to
prevent digital noise pickup.
6. A low noise (jitter) clock signal generator is required for
good ADC dynamic performance. A poor generator can
seriously impair good SNR performance particularly at
higher input frequencies. A high-frequency generator, based
on a clock source (e.g., crystal source), is recommended.
Frequency-synthesized clock generators should generally be
avoided because they typically provide poor jitter perfor-
mance. See Note 8 if a crystal-based clock generator is used
during FFT testing.
A low jitter clock may be generated by using a high-frequency
clock source and dividing this frequency down with a low noise
clock divider to obtain the AD9260 input CLK. Maintaining a
large amplitude clock signal may also be very beneficial in mini-
mizing the effects of noise in the digital gates of the clock gen-
eration circuitry.
Finally, special care should be taken to avoid coupling noise
into any digital gates preceding the AD9260 CLK pin. Short
leads are necessary to preserve fast rise times and careful decou-
pling should be used with these digital gates and the supplies
for these digital gates should be connected to the same supplies
as that of the internal AD9260 clock circuitry (Pins 44 and 38).
7. Two-tone testing will require isolation between test signal
generators to prevent IMD generation in the test generator
output circuits.
8. A very low side-lobe window must be used for FFT calcula-
tions if generators cannot be phase-locked and set to exact
frequencies.
9. A well designed, clean PC board layout will assure proper
operation and clean spectral response. Proper grounding
and bypassing, short lead lengths, separation of analog and
digital signals, and the use of ground planes are particularly
important for high-frequency circuits. Multilayer PC boards
are recommended for best performance, but if carefully
designed, a two-sided PC board with large heavy (20 oz.
foil) ground planes can give excellent results.
10. Prototype
“
plug-boards
”
or wire-wrap boards will not be
satisfactory.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9260ASRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 2.5Msps 16-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:16-BIT HIGH SPEED OVERSAMPLED ADC - Bulk |
| AD9260ASZ | 功能描述:IC ADC CMOS 16BIT OVRSAMP 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9260ASZRL | 功能描述:IC ADC 16BIT 2.5MHZ 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9260EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
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