
AD9260
–11–
REV. B
PIN CONFIGURATION
12 13 14 15 16 17 18 19 20 21 22
3
4
5
6
7
1
2
10
11
8
9
40 39 38
41
42
43
44
36 35 34
37
29
30
31
32
27
28
25
26
23
24
33
PIN 1
TOP VIEW
(Not to Scale)
REFCOM
VREF
SENSE
RESET
AVSS
AVDD
CS
DVSS
AVSS
DVDD
AVDD
DRVSS
DRVDD
CLK
READ
(LSB) BIT16
BIT15
BIT14
DAV
OTR
BIT1 (MSB)
BIT2
AD9260
B
B
A
N
V
V
N
C
A
B
C
C
B
B
M
B
B
B
B
B
B
B
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
2, 29, 38
3
4, 28, 44
5
6
7
8
9
10
–
23
24
25
26
27
30
31
32
33
34
35
36
37
39
40, 43
41
42
DVSS
AVSS
DVDD
AVDD
DRVSS
DRVDD
CLK
READ
BIT16
BIT15
–
BIT2
BIT1
OTR
DAV
CS
RESET
SENSE
VREF
REFCOM
MODE
BIAS
CAPB
CAPT
CML
NC
VINA
VINB
Digital Ground.
Analog Ground.
+3 V to +5 V Digital Supply.
+5 V Analog Supply.
Digital Output Driver Ground.
+3 V to +5 V Digital Output Driver Supply.
Clock Input.
Part of DSP Interface
—
Pull Low to Disable Output Bits.
Least Significant Data Bit (LSB).
Data Output Bit.
Most Significant Data Bit (MSB).
Out of Range
—
Set When Converter or Filter Overflows.
Data Available.
Chip Select (
CS
): Active LOW.
RESET
: Active LOW.
Reference Amplifier SENSE: Selects REF Level.
Input Span Select Reference I/O.
Reference Common.
Mode Select
—
Selects Decimation Mode.
Power Bias.
Noise Reduction Pin
—
Decouples Reference Level.
Noise Reduction Pin
—
Decouples Reference Level.
Common-Mode Level (AVDD/2.5).
No Connect (Ground for Shielding Purposes).
Analog Input Pin (+).
Analog Input Pin (
–
).