參數(shù)資料
型號: AD9260AS
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
中文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝: MS-022AB, MQFP-44
文件頁數(shù): 27/36頁
文件大?。?/td> 572K
代理商: AD9260AS
AD9260
–27–
REV. B
The scaling is accomplished by properly attaching an external
resistor to the BIAS pin of the AD9260 as shown in Table IX.
R
EXT
is normally 2 k
for a clock speed of 20 MHz and scales
inversely with clock rate. Because BIAS is an external pin, mini-
mization of capacitance to this pin is recommended in order to
prevent instability of the bias pin amplifier.
AVDD
4R
3R
2R
R
MODE PIN
AVSS
E
LATCH
CLOCK
ENCODED MODE
Figure 62. Simplified Mode Pin Circuitry
BIAS CURRENT
REXT
BIAS PIN
1V
Figure 63. Simplified Bias Pin Circuitry
POWER DISSIPATION CONSIDERATIONS
The power dissipation of the AD9260 is dependent on its
application-specific configuration and operating conditions.
The analog power dissipation as shown in Figure 64 is primarily
a function of its power bias setting and sample rate. It remains
insensitive to the particular input waveform being digitized or
digital filter MODE setting. The digital power dissipation is
primarily a function of the digital supply setting (i.e., +3 V to
+5 V), the sample rate and, to a lesser extent, the MODE setting
and input waveform. Figures 65a and 65b show the total current
dissipation of the
combined
digital (DVDD) and digital driver
supply (DRVDD) for +3 V and +5 V supplies. Note, DVDD
and DRVDD are typically derived from the same supply bus
since no degradation in performance results. A 1 MHz full-
scale sine wave was used to ensure maximum digital activity in
the digital filters and the digital drivers had a fanout of one.
Note also that a twofold decrease in digital supply current re-
sults when the digital supply is reduced form +5 V to +3 V.
SAMPLE RATE
MSPS
I
A
5
30
70
90
110
130
10
15
20
50
FULL BIAS-2k
HALF BIAS-4k
QUARTER BIAS-8k
Figure 64. I
AVDD
vs. Sample Rate (AVDD = +5 V,
Mode 1
×
–4
×
)
8
2
4
1
SAMPLE RATE
MSPS
I
D
/
D
5
6
10
12
14
16
10
15
20
8
4
2
0
Figure 65a. I
DVDD
/I
DRVDD
vs. Sample Rate (DVDD = DRVDD =
3 V, f
IN
= 1 MHz)
8
2
4
1
SAMPLE RATE
MSPS
I
D
/
D
5
10
20
25
30
10
15
20
15
5
0
Figure 65b. I
DVDD
/I
DRVDD
vs. Sample Rate (DVDD = DRVDD
= 5 V, f
IN
= 1 MHz)
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