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| 型號(hào)： | AD9260AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | MS-022AB, MQFP-44 |
| 文件頁(yè)數(shù)： | 24/36頁(yè) |
| 文件大?。?/td> | 572K |
| 代理商： | AD9260AS |
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AD9260
–24–
REV. B
The outputs of each op amp are ac coupled via a small series
resistor and capacitor (i.e., 50
and 0.1
μ
F) to the respective
inputs of the AD9260. Similar to the dc coupled driver, further
out-of-band noise reduction can be realized with the addition of
100 pF single-ended and differential capacitors, C
S
and C
D
.
The lower-cutoff frequency of this ac coupled circuit is deter-
mined by R
C
and C
C
in which R
C
is tied to the common-mode
level pin, CML, of the AD9260 for proper biasing of the inputs.
Although the OPA642 was found to provide the lowest overall
noise and distortion performance (i.e., 88.8 dB and 96 dB
THD @ 100 kHz), the AD8055 (or dual AD8056) suffered
only a 0.5 dB to 1.5 dB degradation in overall performance. It
is worth noting that given the high-level of performance attainable
by the AD9260, special consideration must be given to both the
quality of the test equipment and test setup in its evaluation.
Common-Mode Level
The CML pin is an internal analog bias point used internally by
the AD9260. This pin must be decoupled to analog ground
with at least a 0.1
μ
F capacitor as shown in Figure 59. The dc
level of CML is approximately AVDD/2.5. This voltage should
be buffered if it is to be used for any external biasing.
Note: the common-mode voltage of the input signal applied to
the AD9260 need not be at the exact same level as CML. While
this level is recommended for optimal performance, the AD9260 is
tolerant of a range of input common-mode voltages around
AVDD/2.5.
CML
AD9260
0.1 F
Figure 59. CML Decoupling
REFERENCE OPERATION
The AD9260 contains an onboard bandgap reference and inter-
nal reference buffer amplifier. The onboard reference provides a
pin-strappable option to generate either a 1 V or 2.5 V output.
With the addition of two external resistors, the user can generate
reference voltages other than 1 V and 2.5 V. Another alterna-
tive is to use an external reference for designs requiring en-
hanced accuracy and/or drift performance. See Table IV for a
summary of the pin-strapping options for the AD9260 reference
configurations.
Note, the optimum noise and distortion can only be
achieved with a 2.5 V reference
.
Figure 60 shows a simplified model of the internal voltage refer-
ence of the AD9260. A pin-strappable reference amplifier
buffers a 1 V fixed reference. The output from the reference
amplifier, A1, appears on the VREF pin and MUST be de-
coupled with 0.1
μ
F and 10
μ
F capacitor to REFCOM. The
voltage on the VREF pin determines the full-scale input span of
the A/D. This input span equals:
Full-Scale Input Span
= 1.6
×
VREF
The voltage appearing at the VREF pin, as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators that monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to REFCOM, the switch is con-
nected to the internal resistor network, thus providing a VREF
of 2.5 V. If the SENSE pin is tied to the VREF pin via a short
or resistor, the switch is connected to the SENSE pin. A short
will provide a VREF of 1.0 V while an external resistor network
will provide an alternative VREF SPAN between 1.0 V and
2.5 V. The external resistor network may, for example, be
implemented as a resistor divider circuit. This divider circuit
could consist of a resistor (R1) connected between VREF and
SENSE and another resistor (R2) connected between SENSE
and REFCOM. The other comparator controls internal cir-
cuitry that will disable the reference amplifier if the SENSE pin
is tied to AVDD. Disabling the reference amplifier allows the
VREF pin to be driven by an external voltage reference.
The reference buffer circuit, level shifts the reference to an
appropriate common-mode voltage for use by the internal cir-
cuitry. The on-chip buffer provides the low impedance neces-
sary for driving the internal switched capacitor circuits and
eliminates the need for an external buffer op amp.
The actual reference voltages used by the internal circuitry of
the AD9260 appear on the CAPT and CAPB pins. If VREF is
configured for 2.5 V, thus providing a 4 V full-scale input span,
the voltages appear at CAPT and CAPB are 3.0 V and 1.0 V
respectively. For proper operation when using the internal or an
external reference, it is necessary to add a capacitor network to
decouple the CAPT and CAPB pins. Figure 61 shows the rec-
ommended decoupling network. This capacitive network per-
forms the following three functions: (1) along with the reference
amplifier, A2, it provides a low source impedance over a large
frequency range to drive the A/D internal circuitry, (2) it pro-
vides the necessary compensation for A2, and (3) it bandlimits
the noise contribution from the reference. The turn-on time of
the reference voltage appearing between CAPT and CAPB is
approximately 15 ms and should be evaluated in any power-
down mode of operation.
LOGIC
LOGIC
–
+
AD9260
1V
DISABLE
A1
TO A/D
5k
5k
A2
6.25k
6.25k
DISABLE
A2
A1
7.5k
5k
CAPT
CAPB
VREF
SENSE
REFCOM
Figure 60. Simplified Reference
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PDF描述 |
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| AD9260EB | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9280ARSRL | Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter |
| AD9280 | Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter |
| AD9280-EB | Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter |
| AD9280ARS | Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9260ASRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 2.5Msps 16-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:16-BIT HIGH SPEED OVERSAMPLED ADC - Bulk |
| AD9260ASZ | 功能描述:IC ADC CMOS 16BIT OVRSAMP 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9260ASZRL | 功能描述:IC ADC 16BIT 2.5MHZ 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9260EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
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