參數(shù)資料
型號: AD7998BRUZ-13
廠商: Analog Devices, Inc.
元件分類: 串行ADC
英文描述: 8-Channel, 10- and 12-Bit ADCs with I2CCompatible
中文描述: 8通道,10 -和12位ADC與I2CCompatible
文件頁數(shù): 8/32頁
文件大?。?/td> 1056K
代理商: AD7998BRUZ-13
AD7997/AD7998
Parameter
t
10
t
11
t
11A
Rev. 0 | Page 8 of 32
Conditions
Standard mode
Fast mode
High speed mode
C
B
= 100 pF max
C
B
= 400 pF max
Standard mode
Fast mode
High speed mode
C
B
= 100 pF max
C
B
= 400 pF max
Standard mode
AD7997/AD7998 Limit at T
MIN
, T
MAX
Max
300
20 + 0.1 C
B
300
10
80
20
160
1000
20 + 0.1 C
B
300
10
40
20
80
1000
Description
t
FDA
, fall time of SDA signal
t
RCL
, rise time of SCL signal
t
RCL1
, rise time of SCL signal after a repeated start
condition and after an Acknowledge bit
t
FCL
, fall time of SCL signal
Pulse width of suppressed spike
Power-up time
Min
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
12
t
SP
t
POWER-UP
Fast mode
High speed mode
C
B
= 100 pF max
C
B
= 400 pF max
Standard mode
Fast mode
High speed mode
C
B
= 100 pF max
C
B
= 400 pF max
Fast mode
High speed mode
20 + 0.1 C
B
10
20
20 + 0.1 C
B
10
20
0
0
1
300
80
160
300
300
40
80
50
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
typ μs
1
A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
2
For 3 V supplies, the maximum hold time with
C
B
= 100 pF max is 100 ns max.
P
S
S
P
t
6
t
4
t
1
t
3
t
5
t
8
t
2
t
11
t
12
t
6
SCL
SDA
t
7
t
9
t
10
S = START CONDITION
P = STOP CONDITION
0
Figure 2. Timing Diagram for 2-Wire Serial Interface
相關(guān)PDF資料
PDF描述
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