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參數(shù)資料
| 型號： | AD7998BRUZ-13 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Channel, 10- and 12-Bit ADCs with I2CCompatible |
| 中文描述： | 8通道，10 -和12位ADC與I2CCompatible |
| 文件頁數(shù)： | 28/32頁 |
| 文件大小： | 1056K |
| 代理商： | AD7998BRUZ-13 |
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AD7997/AD7998
MODES OF OPERATION
When supplies are first applied to the AD7997/AD7998, the
ADC powers up in sleep mode and normally remains in this
shutdown state while not converting. There are three methods
of initiating a conversion on the AD7997/AD7998.
Rev. 0 | Page 28 of 32
MODE 1—USING THE CONVST PIN
A conversion can be initiated on the AD7997/AD7998 by
pulsing the CONVST signal. The conversion clock for the part
is internally generated so no external clock is required, except
when reading from or writing to the serial port. On the rising
edge of CONVST, the AD7997/AD7998 begins to power up (see
point A in Figure 32). The power-up time from shutdown mode
for the AD7997/AD7998 is approximately 1 μs; the CONVST
signal must remain high for 1 μs for the part to power up fully.
CONVST can be brought low after this time. This power-up
time also includes the acquisition time of the ADC. The falling
edge of the CONVST signal places the track-and-hold into hold
mode; a conversion is also initiated at this point (point B in
Figure 32). When the conversion is complete, approximately
2 μs later, the part returns to shutdown (point C in Figure 32)
and remains there until the next rising edge of CONVST. The
master can then read the ADC to obtain the conversion result.
The address pointer register must be pointing to the conversion
result register in order to read back the conversion result.
If the CONVST pulse does not remain high for more than 1 μs,
the falling edge of CONVST still initiates a conversion but the
result is invalid because the AD7997/AD7998 are not fully
powered-up when the conversion takes place. To maintain the
performance of the AD7997/AD7998 in this mode it is
recommended that the I
2
C bus is quiet when a conversion is
taking place.
The cycle timer register and Bits C4 to C1 in the address pointer
register should contain all 0s when operating the AD7997/
AD7998 in this mode. The CONVST pin should be tied low for
all other modes of operation.
To select an analog input channel for conversion in this mode,
the user must write to the configuration register and select the
corresponding channel for conversion. To set up a sequence of
channels to be converted with each CONVST pulse, set the
corresponding channel bits in the configuration register (see
Table 11).
Once a conversion is complete, the master can address the
AD7997/AD7998 to read the conversion result. If further
conversions are required, the SCL line can be taken high while
the CONVST signal is pulsed again; then an additional 18 SCL
pulses are required to read the conversion result.
When operating the AD7997-1/AD7998-1 in Mode 1 and
reading after conversion with a 3.4 MHz f
SCL
, the ADCs can
achieve a typical throughput rate of up to 121 kSPS.
1
1
9
SCA
9
S
7-BIT ADDRESS
R
A
FIRST DATA BYTE (MSBs)
A
SECOND DATA BYTE (LSBs)
9
P
SDA
t
POWER-UP
B
A
C
t
CONVERT
0
CONVST
A
Figure 32. Mode 1 Operation
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