參數(shù)資料
型號(hào)： AD7998BRUZ-13
廠商： Analog Devices, Inc.
元件分類： 串行ADC
英文描述： 8-Channel, 10- and 12-Bit ADCs with I2CCompatible
中文描述： 8通道，10 -和12位ADC與I2CCompatible
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 1056K
代理商： AD7998BRUZ-13
AD7997/AD7998
MODE 2 – COMMAND MODE
This mode allows a conversion to be automatically initiated any
time a write operation occurs. In order to use this mode, the
Command Bits C4 to C1 in the address pointer byte shown in
Table 7 must be programmed.
Rev. 0 | Page 29 of 32
To select a single analog input for conversion in this mode, the
user must set Bits C4 to C1 of the address pointer byte to
indicate which channel to convert on (see Table 26). When all
four command bits are 0, this mode is not in use.
To select a sequence of channels for conversion in this mode,
first select the channels to be included in the sequence by
setting the channel bits in the configuration register. Next, set
the command bits in the address pointer byte to 0111. With the
command bits of the address pointer byte set to 0111, the ADC
knows to look in the configuration register for the sequence of
channels to be converted. The ADC starts converting on the
lowest channel in the sequence and then the next lowest until all
the channels in the sequence are converted. The ADC stops
converting the sequence when it receives a STOP bit.
Figure 29 illustrates a 2-byte read operation from the
conversion result register. This operation is preceded typically
by a write to the address pointer register so that the following
read accesses the desired register, in this case the conversion
result register (see Figure 26). If Command Bits C4 to C1 are set
when the contents of the address pointer register are being
loaded, the AD7997/AD7998 begins to power up and convert
upon the selected channel(s). Power-up begins on the fifth SCL
falling edge of the address point byte, (see point A in Figure 33).
Table 26 shows the channel selection in this mode via
Command Bits C4 to C1 in the address pointer register. The
wake-up, acquisition, and conversion times combined should
take approximately 3 μs. Following the write operation, the
AD7997/AD7998 must be addressed again to indicate that a
read operation is required. The read then takes place from the
conversion result register. This read accesses the conversion
result from the channel selected via the command bits. If
Command Bits C4 to C1 were set to 0111, and Bits D4 and D5
were set in the configuration register, a 4-byte read would be
necessary. The first read accesses the data from the conversion
on V
IN
1. While this read takes place, a conversion occurs on
V
IN
2. The second read accesses this data from V
IN
2. Figure 34
illustrates how this mode operates; the user would first have
written to the configuration register to select the sequence of
channels to be converted before write addressing the part with
the command bits set to 0111.
When operating the AD7997-1/AD7998-1 in Mode 2 with a
high speed mode, 3.4 MHz SCL, the conversion may not be
complete before the master tries to read the conversion result.
If this is the case, the AD7997-1/AD7998-1 holds the SCL line
low during the ACK clock after the read address, until the con-
version is complete. When the conversion is complete, the
AD7997-1/AD7998-1 releases the SCL line and the master can
then read the conversion result.
After the conversion is initiated by setting the command bits
in the address pointer byte, if the AD7997/AD7998 receives a
STOP or NACK from the master, the AD7997/AD7998 stops
converting.
Table 26. Address Pointer Byte
C4
C3
C2
0
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
C1
0
0
1
0
1
0
1
0
1
1
P3
0
0
0
0
0
0
0
0
0
0
P2
0
0
0
0
0
0
0
0
0
0
P1
0
0
0
0
0
0
0
0
0
0
P0
0
0
0
0
0
0
0
0
0
0
Mode 2, Convert On
Not selected
V
IN
1
V
IN
2
V
IN
3
V
IN
4
V
IN
5
V
IN
6
V
IN
7
V
IN
8
Sequence of channels selected in the
configuration register, Bits D11 to D4.
Comments
With the pointer Bits P3–P0 set to all 0s,
the next read accesses the results of the
conversion result register.
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