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參數(shù)資料
| 型號： | AD7998BRUZ-13 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Channel, 10- and 12-Bit ADCs with I2CCompatible |
| 中文描述： | 8通道，10 -和12位ADC與I2CCompatible |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | AD7998BRUZ-13 |
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AD7997/AD7998
CONFIGURATION REGISTER
The configuration register is a 16-bit read/write register that is used to set the operating mode of the AD7997/AD7998. The 4 MSBs of the
register are unused. The bit functions of all 12 LSBs of the configuration register are outlined in Table 9. A 2-byte write is necessary when
writing to the configuration register.
Table 9. Configuration Register Bits and Default Settings at Power-Up
D15
D14
D13
D12
D11 D10
D9
D8
Rev. 0 | Page 19 of 32
D7
D6
D5
D4
D3
D2
ALERT
EN
0
D1
BUSY/
ALERT
0
D0
ALERT/BUSY
POLARITY
0
DONTC DONTC DONTC
0
0
DONTC
0
CH8
0
CH7
0
CH6
0
CH5
0
CH4
0
CH3
0
CH2
0
CH1
0
FLTR
1
0
Table 10. Bit Function Descriptions
Bit
Mnemonic
D11 to D4
CH8 to CH1
Comment
These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D11 to D4
selects a channel for conversion. If more than one channel bit is set to 1, the AD7997/AD7998 sequence
through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Prior
to initiating a conversion, a channel or channels for conversion must be selected in the configuration register.
The value written to this bit of the control register determines whether the filtering on SDA and SCL is
enabled or is to be bypassed. If this bit is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed.
The hardware ALERT function is enabled if this bit is set to 1, and disabled if this bit is set to 0. This bit is used
in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin acts as an ALERT or a BUSY
output (see Table 12).
This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/ BUSY output, Pin 17, acts as
an ALERT or BUSY output (see Table 12), and if Pin 17 is configured as an ALERT output pin, if it is to be reset.
This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is configured as an
ALERT or BUSY output. It is active low if this bit is set to 0, and active high if set to 1.
D3
FLTR
D2
ALERT EN
D1
BUSY/ALERT
D0
BUSY/ALERT
POLARITY
Table 11. Channel Selection
D11
D10
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
D9
0
0
0
0
0
1
0
0
D8
0
0
0
0
1
0
0
0
D7
0
0
0
1
0
0
0
0
D6
0
0
1
0
0
0
0
0
D5
0
1
0
0
0
0
0
0
D4
1
0
0
0
0
0
0
0
Selected Analog Input Channel
Convert on Channel 1 (V
IN
1)
Convert on Channel 2 (V
IN
2)
Convert on Channel 3 (V
IN
3)
Convert on Channel 4 (V
IN
4)
Convert on Channel 5 (V
IN
5)
Convert on Channel 6 (V
IN
6)
Convert on Channel 7 (V
IN
7)
Convert on Channel 8 (V
IN
8)
Comments
If more than one channel is
selected, the AD7997/AD7998
start converting on the selected
sequence of channels starting with
the lowest channel in the
sequence.
Table 12. ALERT/BUSY Function
D2
D1
0
0
0
1
1
0
ALERT/BUSY Pin Configuration
Pin does not provide any interrupt signal.
Pin configured as a BUSY output.
Pin configured as an ALERT output.
Resets the ALERT output pin, the Alert_Flag bit in the conversion result register, and the entire alert status register
(if any is active). If 1/1 is written to Bits D2/D1 in the configuration register to reset the ALERT pin, the Alert_Flag bit,
and the alert status register, the contents of the configuration register read 1/0 for D2/D1, respectively, if read back.
1
1
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