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參數(shù)資料
| 型號： | AD6652BC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 8/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BC |
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AD6652
GENERAL TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise specified.
Table 6.
Parameter (Conditions)
CLK TIMING REQUIREMENTS
t
CLK
CLK Period
t
CLKL
CLK Width Low
t
CLKH
CLK Width High
RESET TIMING REQUIREMENTS
t
RESL
RESET Width Low
LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS
t
DLI
↑
CLK to LI (LIA, LIA; LIB, LIB) Output Delay Time
SYNC TIMING REQUIREMENTS
t
SS
SYNC(A,B,C,D) to
↑
CLK Setup Time
t
HS
SYNC(A,B,C,D) to
↑
CLK Hold Time
PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE)
Switching Characteristics
1
t
DPOCLKL
↓
CLK to
↑
PCLK Delay (Divide-by-1)
t
DPOCLKLL
↓
CLK to
↑
PCLK Delay (Divide-by-2, -4, or -8)
t
DPREQ
↑
PCLK to
↑
PxREQ Delay
t
DPP
↑
PCLK to Px[15:0] Delay
Input Characteristics
t
SPA
PxACK to
↓
PCLK Setup Time
t
HPA
PxACK to
↓
PCLK Hold Time
PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE)
Switching Characteristics
1
t
POCLK
PCLK Period
t
POCLKL
PCLK Low Period (when PCLK Divisor = 1)
t
POCLKH
PCLK High Period (when PCLK Divisor = 1)
t
DPREQ
↑
PCLK to
↑
PxREQ Delay
t
DPP
↑
PCLK to Px[15:0] Delay
Input Characteristics
t
SPA
PxACK to
↓
PCLK Setup Time
t
HPA
PxACK to
↓
PCLK Hold Time
LINK PORT TIMING REQUIREMENTS
Switching Characteristics
1
t
RDLCLK
↑
PCLK to
↑
LxCLKOUT Delay
t
FDLCLK
↓
PCLK to
↓
LxCLKOUT Delay
t
RLCLKDAT
↑
LCLKOUT to Lx[7:0] Delay
t
FLCLKDAT
↓
LCLKOUT to Lx[7:0] Delay
Rev. 0 | Page 8 of 76
Temp
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
Min
15.4
6.2
6.2
30.0
3.3
Typ
t
CLK
/2
t
CLK
/2
Max
10.0
Unit
ns
ns
ns
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
2.0
1.0
6.5
8.3
7.0
3.0
12.5
2.0
2.0
1.0
1.0
0
0
0.5 × t
POCLK
0.5 × t
POCLK
10.5
14.6
1.0
0.0
10.0
11.0
2.5
0
2.9
2.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
The timing parameters for Px[15:0], PxREQ, and PxACK apply for Port A and B (x stands for A or B).
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
| AD6652BC/PCBZ | 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHA 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHANNEL RSP - Bulk |
| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652XBC | 制造商:Analog Devices 功能描述:- Bulk |
| AD6653 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
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