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參數(shù)資料
| 型號： | AD6652BC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 13/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BC |
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AD6652
Pin No.
DDC OUTPUTS
B11
C11
C12
P8
B3
Rev. 0 | Page 13 of 76
Mnemonic
Type
Function
LIA
LIA
LIB
LIB
PACH0_LACLKOUT
2
Output
Output
Output
Output
Output
Level Indicator, Input A, Data A.
Level Indicator, Input A, Data A.
Level Indicator, Input B, Data B.
Level Indicator, Input B, Data B.
Channel ID Output Bit, LSB, for Parallel Port A, or Link Port A Clock Output.
Function depends on logic state of 0x1B:7 of output port control register.
Channel ID Output Bit, LSB, for Parallel Port B, or Link Port B Clock Output.
Function depends on logic state of 0x1D:7 of output port control register.
Link Port A Data or Parallel Port A Data [7:0], Eight Pins.
R2
PACH0_LBCLKOUT
2
Output
F1, D1, D2,
C2, B2, E2,
A4, A2
P2, R3, N3,
M2, M3, T3,
L1, L2
E1, C1, F3,
G2, G1, G3,
H3, H2
P3, R4, P4,
T4, R5, T5,
P5, R6
N1
R1
PARALLEL OUTPUT PORT CONTROL
K2
PAACK
H1
PAREQ
P7
PBACK
T6
PBREQ
MICROPORT CONTROL
C5, A5, C6,
A6, B7, C7,
B8, C8
B4, C3, A3
A[2:0]
C4
DS(RD)
4
PA[7:0]_LA[7:0]
Output
PB[7:0_LB[7:0]
Output
Link Port B Data or Parallel Port B Data [7:0], Eight Pins.
PA[15:8]
Output
Parallel Port A Data [15:8], Eight Pins.
PB[15:8]
Output
Parallel Port B Data [15:8], Eight Pins.
PAIQ
PBIQ
Output
Output
Parallel Port A I or Q Data Indicator, I = High, Q = Low.
Parallel Port B I or Q Data Indicator, I = High, Q = Low.
Input
Output
Input
Output
Parallel Port A Acknowledge.
Parallel Port A Request.
Parallel Port B Acknowledge.
Parallel Port B Request.
D[7:0]
I/O
Bidirectional Microport Data, Eight Pins. This bus is three-stated when CS is high.
Input
Input
Microport Address Bus, 3 Pins.
Function depends upon MODE pin.
Active Low Data Strobe when MODE = 1.
Active Low Read Strobe when MODE = 0.
Function depends upon MODE pin.
Active Low Data Acknowledge when MODE = 1.
Microport Status Pin when MODE = 0.
Read/Write Strobe when MODE = 1. Active Low Write strobe when MODE = 0.
Mode Select Pin. 0 = Intel mode, 1 = Motorola mode.
Active Low Chip Select. Logic 1 three-states the microport data bus.
C9
DTACK(RDY)
4,
Output
B6
A9
A7
R/W (WR)
4
MODE
4
CS
3
Input
Input
Input
1
PDWN pins must be the same logic level: both logic high or both logic low.
2
PACH0 and PACH1 form a 2-bit output word in the parallel output mode that identifies the processing channel (0, 1, 2, or 3) whose data appears on Port A parallel
outputs. Likewise, PBCH0 and PBCH1 identify the channel for Port B.
3
Pins with a pull-down resistor of nominal 70 k.
4
Mode 0 is Intel nonmultiplexed (IMN), and Mode 1 is Motorola nonmultiplexed (MNM). Pin logic level corresponds to mode.
5
Pins with a pull-up resistor of nominal 70 k.
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相關代理商/技術參數(shù) |
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