參數(shù)資料
型號(hào)： AD6652BC
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： 12位，65 MSPS的IF到基帶分集接收機(jī)
文件頁(yè)數(shù)： 56/76頁(yè)
文件大小： 1839K
代理商： AD6652BC
AD6652
ACCESS CONTROL REGISTER (ACR)
External Address 7
The ACR specifies certain programming characteristics such as
autoincrement or broadcast, which are to be applied to the
incoming instructions, and selects which channel(s) are to be
programmed by th
Rev. 0 | Page 56 of 76
e microport or serial port.
,
it 6 of the register is the broadcast bit, which determines how
B
Bits 5–2 are interpreted. If broadcast is 0 the
are referred to as instruction bits (Instructio
compared with the
IP_ID[3:0
matche
[3:0] pins determines the acce
allo
o be connected to
mem
out external logic. This also
sa
os
n Bits 5–2, which
n[3:0]), are
CH
] pins. The instruction that
s the CHIP_ID
ws up to 16 chips t
ory mapped with
me serial port of a h t processor to configure up to 16 chips.
ss. This
the same port and
allows the
the broadcast bit is h h, the Instruction[3:0] word allows
ultiple AD6652 chan els and/or chips to be configured
ultaneously indepe
ossible instruction
smart antenna syst
gle antenna or car
x’s in the commen
s” in the digital de
h) readback is n
ternal bus contentio
erefore, if readback is subsequently
ed, the broadcast t should be set low.
desir
bi
3:0] pins. The
eful
ls listening to
ltaneously.
ent “don’t
t is enabled (Bit 6
otential for
its 1–0 of the ACR ar address bits that decode which of the
ur channels are bein
sed. If the instruction bits decode
n access to multiple c
nnels, then these bits are ignored. If the
struction decodes an a
bits otherwise d
the channel being accessed.
Instructions,
ruction
Comm
Inst
ent
0000
All chips and all
channe
0001
Channe 0, 1, 2 of all chips have access.
ls
0010
Channe
ls 1, 2, 3 of all chi
0100
All chips get the access.
1
1000
All chip
s with Chip_ID[3:0] =
1001
All chip
s with Chip_ID[3:0] = x
1100
All chip
s with Chip_
1101
All chip
s with Chip
1110
All chip
ip_ID[3:0] = xx10 have access.
1
s with Ch
1111
All chip
s with Chip_ID[3:0] =
Bit 7 of this register is the autoincrement bit. If this bit is a 1
then the CAR register, described in the Channel Address
Register (CAR) section, increments its value after every access
to the channel. This allows blocks of address space such as
coefficient memory to be initialized more efficiently.
If
m
sim
10 p
for
a sin
The
care
et hig
s
in
ig
ndent of the CHIP_ID[
s are defined in Table 23. This is us
ems, where multiple channe
rier can be configured simu
t portion of the table repres
coding. When broadcas
ecause of the p
ot valid b
n. Th
B
fo
a
in
A[9:8]
Table 23. Microport
g acces
ha
etermine
7:5–2
ls have access.
ps have access.
xxx0 have access.
1
xx1 have access.
1
ID[3:0] = xx00 have access.
1
_ID[3:0] = xx01 have access.
1
xx11 have access.
1
1
A[9:8] bits control which c
.
f a channel register
autoincrement bit of the
the
by
er
gister also contains
BIST (built-in self-test) commands that turn internal test
signals off or on, namely, pseudonoise and negative full-scale
e wav
d 6, explained below.
sin
e, at Bits 7 an
Bits 0–3
for each
or all of
recipien
signal is
below. A
signal, if
SOFT_SYNC channel enable bits
r DDC channels. Writing a logic hig
simply
t_sync sy
by Bits 4 and 5 o
signal can
he fou
e bits
a sof
erated
h to one
selects the indicated channel(s) to be
nchronizing pulse—whenever such
f this register as described
be used in addition to a soft-sync
nc
ired.
Bit 4 is t
logic hig
hold-of
Bits 3–0
for furth
Channel
ng pulse. Writing this bit to
ot-type pulse to trigger the start
cted DDC channels according to
nnel/Chip Synchronization section
it also programs
ation. Programming this b
ister 0x82 of each channel.
s Reg
Bit 5 is t
logic hig
frequen
accordin
Synchro
the Cha
op so
iate
old-o
Bits
tion s
Addr
his bit to
hop
nnels
hannel/Chip
mming this bit also programs
ection. Progra
ess Register 0x82 of each channel.
Bit 6 co
this bit is lo
connect
this is n
internal
purpose
choice.
register.
w the internal
input data bus is configured. If
the ADCs (analog–to-digital converters) are
w, then
ed to
DDC NCOs according to the
orma
ration. If this bit is logic high
test si
ls are connected to a
s and
overrides any NCO
The internal test signals are configur
the
l ope
gna
this
user’s choice—
, then the
ll DDC NCOs for BIST
programmed input
ed in Bit 7 of this
If Bit 7
made av
the inte
data is a
function
conjunc
in-syste
ow
nal is generated and
f this bit is high, then
al pseudorandom noise generator is enabled and this
the internal input data bus. The combined
its 6 and 7 facilitate BIST functions. Also, in
e MISR registers, this allows for detailed
testing.
m chip
hannel is decoded for access
CHANNEL ADDRESS REGISTER (CAR)
External Address 6
The user writes the 8-bit internal address o
to be programmed in the CAR. If the
ACR is 1, then this value is incremented after every access to
DR0 register, which in turn accesses the location pointed to
this address. The channel address register cannot be read back
while the broadcast bit is set high.
SOFT_SYNC CONTROL REGISTER
External Address 5
The SOFT_SYNC control register is write only. The regist
name is somewhat deceiving in that this re
of this register are the
of t
thes
ts of
gen
pin-sy
des
he start software synchronizi
h initiates a one-sh
f counter of the sele
above. See the Cha
form
er in
Addres
he h
h init
cy h
g to
niza
nnel
ftware synchronizing pulse. Writing t
s a one-shot-type pulse to trigger the
ff counter of the selected DDC cha
3–0 above. See the C
nfigures ho
is logic l
ailable to the internal data bus. I
rn
vailable to
s of B
tion with th
, a negative full-scale sig
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