參數(shù)資料
型號： AD6652BC
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： 12位，65 MSPS的IF到基帶分集接收機
文件頁數(shù)： 57/76頁
文件大小： 1839K
代理商： AD6652BC
AD6652
PIN_SYNC CONTROL REGISTER
rnal Address 4
he write-only N_SYNC control register.
This is t
PI
Rev. 0 | Page 57 of 76
its 3–0 of this register are the PIN SYNC_EN control bits.
hese bits can be writt
o by the controller to select any or all
f the external pin syn inputs: A, B, C, and/or D. One pin can
e assigned to all channels, one pin can be assigned to one
nnel, or any combination in between. This register is fully
nfigurable at the channel level (in the channel address register
emory map, 0x88) as to which pin-sync signal is selected. A
sync signal can be
red. See Figure 53.
desi
-sync signal, if
is the start enable
tates the routin
DC channels. This b enables any pin-sync signals that were
ted by Bits 3–0 ab
ltimately chosen
ntrols the start function. See Figure 53. Programming this bit
o programs the Cha nel Address Register 0x82 of each
nel.
chan
h enables
nal to
all
the
-1 multiplexer
nc signal that
it 5 is the hop enable bit. Writing this bit to logic high enables
B
or facilitates the routing of the extern
DDC channels. This bit enables any pi
selected by Bits 3–0 above to be routed to a 4-to-1 multiplexer
and ultimately chosen to be the channel’s pin-sync signal that
controls the Hop function. See Figure 53. Programming this bit
also programs the Channel Address Register 0x82 of each
channel.
al pin-sync signal to
all
the
n-sync signals that were
synchronization signals. If this
e
o programs the
External Address 3
In addition to sleep mode control, this register also provides
access to th
e output port control register’s memory map.
control
w, the ch
icated channel enters a low-p
ng this bit als
ach channel.
of e
mode
nel. If the
nel operates n
an
ally. If the bit is high, the
er sleep mode. Program-
nnel Address Register 0x82
Cha
rograms the
o p
Bit 5 allows access to the output control port registers. When
this bit
, the
Howeve
hen th
port con
egist
Externa
dress
output c
ol po
address
er m
Control Registers
section.
gisters are accessed.
the output
igh, the value in
mory map for the
f the normal channel
Table 29 in the Output Port
Bit 6–7 e reserv
ar
w.
DATA
Externa
These r
respecti
to or les
triggers
indicate
internal
last. At t
indicate in A[9:0
directio Once th
must be
DR2 is only 4 bits wide. Data written to the upper 4 bits of this
register are ignored. Likewise, reading from this register
produces only 4 LSBs.
ES
ess 2–0
rm the
data registers DR2, DR1, and DR0,
l in
0
al Address 0 is written to, it
ntern
6652 based on the address
the A
s, during writes to the
sters,
int,
d to the internal memory
his po
data is transferre
]. Reads are performed i
n.
e address is set, Externa
the fi
ata register read to initiate an
S
ual
e written
n the opposite
l Address [0] DR0
internal access.
rst d
sed via this same location by
e
access to
or all four
r can overwrite the data in 0x80, if
ep mode is selected when this bit is written logic
Exte
B
T
o
b
cha
co
m
pin-
en t
c
used in addition to a soft
Bit 4
r facili
o
D
selec
and u
co
als
bit. Writing this bit to logic hig
of the external pin-sync sig
g
it
ove, to be routed to a 4-to
be the channel’s pin-sy
to
Bit 6 is used to ignore repetitive
bit is clear, each PIN_SYNC restarts or frequency hops th
channel. If this bit is set, then only the first occurrence causes
the action to occur. Programming this bit als
Channel Address Register 0x82 of each channel.
Bit 7 is reserved; the bits should be written to Logic 0.
SLEEP CONTROL REGISTER
Bits 3–0
bit is lo
ind
mi
the sleep
of the indicated chan
orm
ow
Bit 4 is reserved and should be written to Logic 0.
is low
r, w
trol r
l Ad
ontr
regist
channel address re
is bit is set high, it allows access to
ers. When this bit is set h
6 (CAR) points to the me
rt registers instead o
emory map. See
ed and should be written lo
ADDR
l Addr
egisters fo
vely. Al
s than 2 bits. When Extern
an i
al access to the AD
d in
CR and CAR. Thu
regi
External Address [0] DR0 must b
S REGISTER
ternal data-words have widths that are eq
Figure 63 is a block diagram of the memory structure.
CHANNEL ADDRESS REGISTERS (CAR)
0x00–0x7F: Coefficient Memory (CMEM)
This register is the coefficient memory (CMEM) used by the
RCF. It is memory mapped as 128 words by 20 bits. A second
128 words of RAM can be acces
writing Bit 8 of the RCF control register high at Channel
Address 0xA4. The filter calculated always uses the same
coefficients for I and Q. By using memory from both of thes
128 blocks, a filter of up to 160 taps can be calculated. Multiple
filters can be loaded and selected with a single internal
the coefficient offset register at Channel Address 0xA3.
0x80: Channel Sleep Register
This register contains the sleep bit for the channel. It mimics the
programming of Bits 0–3 at External Address 3. External
Address 3 provides simultaneous sleep mode control f
DDC channels. The use
desired. Sle
high.
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