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參數(shù)資料
| 型號： | AD6652BC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機(jī) |
| 文件頁數(shù)： | 70/76頁 |
| 文件大小： | 1839K |
| 代理商： | AD6652BC |
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AD6652
Bit 0 selects which data i
Bit 0 = 0, Link Port A outputs data from the
the format specified by Bit 1. When Bit 0 = 1, Link Port A
outputs the data from the AGCs according to the format
specified by
Rev. 0 | Page 70 of 76
s output on Link Port A. When
RCF according to
Bits 1 and 2.
Bit 1 has two different meanings, depending on whether data is
coming from the AGCs or from the RCFs. When data is coming
from the RCFs (Bit 0 = 0), Bit 1 selects between two and four
channel data mode. Bit 1 = 1 indicates that Link Port A
transmits RCF IQ words alternately from Channels 0 and 1.
When Bit 1 = 1, Link Port A outputs RCF IQ words from each
of the four channels in succession: 0, 1, 2, 3. However, when
AGC data is selected (Bit 0 = 1), Bit 1 selects the AGC data
output mode. In this mode, when Bit 1 = 1, Link Port A outputs
AGC A IQ and gain words. With this mode, gain words must
included by setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, the
AGC A and AGC B are alternately output on Link Port A and
the inclusion or exclusion of the gain words is determined by
Bit 2.
be
n
I
it 0 = 0), then this
rammable delay value for Link Port A
ing frequency and
nd the TigerSHARC link port.
k
lel
t data modes for interfacing with DSPs or
from the RCF according
to the format specified by Bits 1–4. When Bit 0 = 1, Parallel
Port B outputs the data from the AGCs according to the format
specified by Bits 1 and 2.
In AGC mode, Bit 0 = 1 and Bit 1 determines if Parallel Port B is
able to output data from AGC A. Bit 2 determines if Parallel
Port B is able to output data from AGC B. The order of output
depends on the rate of triggers from each AGC, which in turn is
determined by the decimation rate of the channels feeding it. In
channel mode, Bit 0 = 0 and Bits 1–4 determine which
combination of the four processing channels is output. The
output order depends on the rate of triggers received from each
channel, which is determined by the decimation rate of each
channel. The channel output indicator pins can be used to
determine which data came from which channel.
This means that I and Q data are interleaved and the IQ indica-
tor pin determines whether data on the port is I data or Q data.
When Bit 5 = 1, Parallel Port B is outputting an 8-bit I word and
an 8-bit Q word at the same time, and the IQ indicator pins are
high.
0x1D: Link Port Control B
Data is output through either a parallel port interface or a link
port interface. The link port provides an efficient data link
between the AD6652 and a TigerSHARC DSP and can be
enabled by setting 0x1D, Bit 7 = 1.
Bit 0 selects which data is output on Link Port B. When
Bit 0 = 0, Link Port B outputs data from the RCF according to
the format specified by Bit 1. When Bit 0 = 1, Link Port B
outputs the data from the AGCs according to the format
cif
spe
ied by Bits 1 and 2.
Bit 1
com
from
channel data mode. Bit 1 = 1 indicates that Link Port A
transmits RCF IQ words alternately from Channels 0 and 1.
When Bit 1 = 1, Link Port B outputs RCF IQ words from each
of the four channels in succession: 0, 1, 2, 3. However, when
AGC data is selected (Bit 0 = 1), Bit 1 selects the AGC data
output mode. In this mode, when Bit 1 = 1, Link Port B outputs
AGC B IQ and gain words. With this mode, gain words must be
included by setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, then
AGC A and B are alternately output on Link Port B and the
inclusion or exclusion of the gain words is determined by Bit 2.
ng
tp
two
word
quad
bit c
Bits
between the time the link port receives a data ready from the
receiver and the time it transmits the first data-word. The link
port must wait at least six cycles of the receiver’s clock, so this
value allows the user to use clocks of differing frequency and
phase for the AD6652 link port and the TigerSHARC link port.
For details on the limitations and relationship of these clocks,
see the Link Port section.
lue for Link Port B
Bit 2 determines if RSSI words are included or not in the data
output. If Bit 1 = 1, Bit 2 = 0. Because the RSSI words are only
two bytes long and the IQ words are four bytes long, the RSS
words are padded with zeros to give a full 16-byte TigerSHARC
quad-word. If AGC output is not selected (B
bit can be any value.
Bits 6–3 specify the prog
between the time the link port receives a data ready from the
receiver and the time it transmits the first data-word. The link
port must wait at least 6 cycles of the receiver’s clock, so this
value allows the user to use clocks of differ
phase for the AD6652 link port a
For details on the limitations and relationship of these clocks,
see the Link Port section.
0x1C: Parallel Port Control B
Data is output through either a parallel port interface or a lin
port interface. When 0x1D, Bit 7 = 0, the use of Link Port B is
disabled and the use of Parallel Port B is enabled. The paral
port provides differen
FPGAs.
Bit 0 selects which data is output on Parallel Port B. When
Bit 0 = 0, Parallel Port B outputs data
Bit 5 determines the format of the output data words. When
Bit 5 = 0, Parallel Port B outputs 16-bit words on its 16-bit bus.
has two different meanings that depend on whether data is
ing from the AGCs or from the RCFs. When data is comi
the RCFs (Bit 0 = 0), Bit 1 selects between two and four
Bit 2 determines whether gain words are included in the data
ou ut. If Bit 1 = 1, Bit 2 = 0. Because the gain words are only
bytes long and the IQ words are four bytes long, the gain
s are padded with zeros to give a full 16-byte TigerSHARC
-word. If AGC output is not selected (Bit 0 = 0), then this
an be any value.
6–3 specify the programmable delay va
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| AD6652PCB | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
| AD6652BC/PCBZ | 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHA 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHANNEL RSP - Bulk |
| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652XBC | 制造商:Analog Devices 功能描述:- Bulk |
| AD6653 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
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