參數(shù)資料
型號(hào): AD6652BC
廠商: Analog Devices, Inc.
英文描述: 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述: 12位,65 MSPS的IF到基帶分集接收機(jī)
文件頁數(shù): 17/76頁
文件大小: 1839K
代理商: AD6652BC
AD6652
DDC TIMING DIAGRAMS
Rev. 0 | Page 17 of 76
LIA, LIB
LIA, LIB
CLK
t
DLI
t
CLKH
t
CLKL
t
CLK
0
Figure 17. Level Indicator Output Switching Characteristics
RESET
t
RESL
0
Figure 18. Reset Timing Requirements
t
HS
t
SS
CLK
SYNCA
SYNCB
SYNCC
SYNCD
0
Figure 19. SYNC Timing Inputs
CLK
PCLK
t
DPOCLKL
0
Figure 20. PCLK to CLK Switching Characteristics Divide-by-1
CLK
PCLK
t
DPOCLKLL
t
POCLKL
t
POCLKH
0
Figure 21. PCLK to CLK Switching Characteristics Divide-by-2, -4, or -8
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