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參數(shù)資料
| 型號： | AD6816 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 483K |
| 代理商： | AD6816 |
a
155 Mbps UTP#5
Complete PHY Interface
AD6816
within the IC allow the user to perform loop-back, bypass the
data retiming function and select the frequency reference for the
transmit bit clock (independent timing or loop timing).
The line equalization and baseline restoration block compensates
for up to 110M Category #5 UTP and transformer, respectively.
This block has a Signal Detect output, SDOUT, that when low in-
dicates a loss of input signal at RX, RXN. The AD6816 supports
application with a fiber optic receiver or transceiver. In this case,
the line equalizer block adapts to provide no equalization.
The line driver has a differential ECL input stage providing con-
trolled current output suitable for driving a Category #5 UTP
system. A single resistor from the line driver output current control
pin to ground controls the output current. The user has the op-
tion to disable the line driver output. A signal multiplexer allows
the user to loop back the line driver input signal through the
clock recovery and data retiming PLL for test purposes.
The clock recovery and data retiming PLL has a factory trimmed
VCO center frequency and an integrated frequency control loop
that combine to ensure signal acquisition. This eliminates reli-
ance on external components, like a crystal or an SAW filter, to
aid frequency acquisition. At frequency lock, the frequency error
is zero and the frequency detector has no effect. At this point,
the PLL works to ensure that the output phase tracks the input
(
Continued on page 4)
FEATURES
Complete ATM Transceiver for 155 Mbps for UTP#5
or Fiber
Meets ATM Forum UNI 3.1 Requirements
Meets SONET/SDH Jitter Requirements
Meets FCC Class B Emissions Requirements
Drives up to 110M Category #5 UTP/FTP
Adjustable Line Driver Output Current
Equalizes up to 110M Category #5 UTP/FTP
Baseline Restoration Function Eliminates Baseline Wander
19.44 MHz Oscillator Circuit
Frequency Synthesizer for 155 MHz Tx Bit Clock
155 Mbps Clock Recovery and Data Retiming
Phase Continuous Switch at Frequency Synthesizer Output
Single Supply Operation: +5 V or –5.2 V
Low Power: 400 mW
10KH ECL Compatible Output
Package: 44-Pin Thin Quad Flatpack
FUNCTIONAL BLOCK DIAGRAM
T
D
D
X
X
O
F
E
E
R
C
C
AD6816
TX
TXN
RX
RXN
CEQ1
CEQ2
SDOUT
DRVROFF
TXCLKOUT
TXCLKOUTN
RXCLKOUT
RXDATOUTN
RXDATOUT
RXCLKOUTN
L
C
C
D
155MHz
FREQUENCY
SYNTHESIZER
DIVIDE
BY 8
MUX
19.44 MHz
OSCILLATOR
MUX
CLOCK RECOVERY
AND
DATA RETIMING
PHASE-LOCKED LOOP
MUX
EQUALIZER,
BASELINE
RESTORATION
AND LOS
LINE
DRIVER
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
PRODUCT DESCRIPTION
The AD6816 provides a single chip solution for interfacing an
ATM User-Network Interface IC to either a Category #5
Unshielded Twisted Pair (UTP) system or a fiber optic system.
The IC provides line equalization and baseline restoration, line
driver, clock recovery and data retiming, local reference clock
oscillator and frequency synthesis functions. Signal multiplexers
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