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參數(shù)資料
| 型號： | A1020B-CQ84C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84 |
| 封裝： | CERAMIC, CQFP-84 |
| 文件頁數(shù)： | 53/54頁 |
| 文件大小： | 333K |
| 代理商： | A1020B-CQ84C |
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RadTolerant FPGAs
1- 4
v3.1
The RT1020 Logic Module
The RT1020 logic module is an 8-input, 1-output logic
circuit chosen for the wide range of functions it
implements and for its efficient use of interconnect
routing resources (Figure 1-3).
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two,
three, or four inputs. Each function may have many
versions, with different combinations of active low
inputs. The logic module can also implement a variety of
D-latches, exclusivity functions, AND-ORs, and OR-ANDs.
No dedicated hardwired latches or flip-flops are required
in the array, since latches and flip-flops may be
constructed from logic modules wherever needed in the
application.
I/O Modules
I/O modules provide the interface between the device
determined by a library macro selection, can be
implemented in the module (refer to the Macro Library
Guide for more information). I/O modules contain a
tristate buffer, and input and output latches that can be
configured for input, output, or bidirectional pins
The RadTolerant devices contain flexible I/O structures in
that each output pin has a dedicated output enable
control. The I/O module can be used to latch input and/or
output data, providing a fast setup time. In addition, the
Actel Designer software tools can build a D-flip-flop,
using a C-module, to register input and/or output
signals.
The Actel Designer software development tools provide
a design library of I/O macros. The I/O macro library
provides macro functions that can implement all I/O
configurations supported by the RadTolerant FPGAs.
Routing Structure
The RadTolerant device architecture uses vertical and
horizontal routing tracks to interconnect the various
logic and I/O modules. These routing tracks are metal
interconnects that may either be of continuous length or
broken into segments. Varying segment lengths allow
over 90% of the circuit interconnects to be made with
only two antifuse connections. Segments can be joined
together at the ends, using antifuses to increase their
length
up
to
the
full
length
of
the
track.
All
interconnects can be accomplished with a maximum of
four antifuses.
Horizontal Routing
Horizontal channels are located between the rows of
modules, and are composed of several routing tracks.
The horizontal routing tracks within the channel are
divided into one or more segments. The minimum
horizontal segment length is the width of a module-pair,
and the maximum horizontal segment length is the full
length of the channel. Any segment that spans more
than one-third the row length is considered a long
horizontal segment. A typical channel is shown in
Non-dedicated
horizontal
routing tracks are used to route signal nets. Dedicated
routing tracks are used for the global clock networks,
and for power and ground tie-off tracks.
Vertical Routing
Another set of routing tracks runs vertically through the
module. There are three types of vertical tracks that can
be divided into one or more segments: input, output,
and long. Each segment in an input track is dedicated to
the input of a particular module. Each segment in an
Figure 1-3 RT1020 Logic Module
Figure 1-4 I/O Module
G/CLK*
QD
EN
PAD
* Can be configured as a Latch or D-Flip-Flop
From Array
To Array
(Using C-Module)
G/CLK*
QD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1020B-CQ84E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1020B-CQ84M | 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 84CQFP |
| A1020B-PG84B | 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 1 2K GATES 547 CELLS 48MHZ 1.0UM 5V 84CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CPGA MIL |
| A1020B-PG84C | 功能描述:IC FPGA 2K GATES 84-CPGA COM RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 1 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A1020B-PG84E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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