參數(shù)資料
型號(hào): A1020B-CQ84C
元件分類(lèi): FPGA
英文描述: FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84
封裝: CERAMIC, CQFP-84
文件頁(yè)數(shù): 15/54頁(yè)
文件大?。?/td> 333K
代理商: A1020B-CQ84C
RadTolerant FPGAs
1- 18
v3.1
Table 1-11 RT1020, A1020B Output Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
Std Speed
Parameter
Description
Min.
Max.
Units
Global Clock Network
tCKH
Input Low to High
FO = 16
FO = 128
6.0
6.9
ns
tCKL
Input High to Low
FO = 16
FO = 128
7.9
8.7
ns
tPWH
Minimum Pulse Width High
FO = 16
FO = 128
8.0
8.4
ns
tPWL
Minimum Pulse Width Low
FO = 16
FO = 128
1.5
2.2
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
1.5
2.3
ns
tP
Minimum Period
FO = 16
FO = 128
16.3
17.5
ns
fMAX
Maximum Frequency
FO = 16
FO = 128
60
50
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
8.3
ns
tDHL
Data to Pad Low
9.3
ns
tENZH
Enable Pad Z to High
8.1
ns
tENZL
Enable Pad Z to Low
9.8
ns
tENHZ
Enable Pad High to Z
12.3
ns
tENLZ
Enable Pad Low to Z
11.1
ns
dTLH
Delta Low to High
0.07
ns/pF
dTHL
Delta High to Low
0.10
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
9.8
ns
tDHL
Data to Pad Low
7.9
ns
tENZH
Enable Pad Z to High
7.4
ns
tENZL
Enable Pad Z to Low
10.2
ns
tENHZ
Enable Pad High to Z
12.3
ns
tENLZ
Enable Pad Low to Z
11.1
ns
dTLH
Delta Low to High
0.13
ns/pF
dTHL
Delta High to Low
0.07
ns/pF
Notes:
1. Delays based on 35pF loading.
2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
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