參數(shù)資料
型號(hào)： A1020B-CQ84C
元件分類： FPGA
英文描述： FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84
封裝： CERAMIC, CQFP-84
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 333K
代理商： A1020B-CQ84C
RadTolerant FPGAs
1- 28
v3.1
RT14100A, A14100A Timing Characteristics
Table 1-21 RT14100A, A14100A Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
3.0
3.5
ns
tCO
Sequential Clock-to-Q
3.0
3.5
ns
tCLR
Asynchronous Clear-to-Q
3.0
3.5
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.3
1.5
ns
tRD2
FO=2 Routing Delay
1.9
2.1
ns
tRD3
FO=3 Routing Delay
2.1
2.5
ns
tRD4
FO=4 Routing Delay
2.6
2.9
ns
tRD8
FO=8 Routing Delay
4.2
4.9
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
1.0
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.6
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.6
ns
tWASYN
Asynchronous Pulse Width
4.8
5.6
ns
tWCLKA
Flip-Flop Clock Pulse Width
4.8
5.6
ns
tA
Flip-Flop Clock Input Period
9.9
11.6
ns
fMAX
Flip-Flop Clock Frequency
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad-to-Y
4.2
4.9
ns
tICKY
Input Reg IOCLK Pad-to-Y
7.0
8.2
ns
tOCKY
Output Reg IOCLK Pad-to-Y
7.0
8.2
ns
tICLRY
Input Asynchronous Clear-to-Y
7.0
8.2
ns
tOCLRY
Output Asynchronous Clear-to-Y
7.0
8.2
ns
Input Module Predicted Routing Delays2, 3
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
1.9
2.1
ns
tIRD3
FO=3 Routing Delay
2.1
2.5
ns
tIRD4
FO=4 Routing Delay
2.6
2.9
ns
tIRD8
FO=8 Routing Delay
4.2
4.9
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4ns.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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