參數(shù)資料
型號(hào)： A1020B-CQ84C
元件分類(lèi)： FPGA
英文描述： FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84
封裝： CERAMIC, CQFP-84
文件頁(yè)數(shù)： 16/54頁(yè)
文件大?。?/td> 333K
代理商： A1020B-CQ84C
RadTolerant FPGAs
v3.1
1-19
RT1280A, A1280A Timing Characteristics
Table 1-12 RT1280A, A1280A Logic Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
5.2
6.1
ns
tCO
Sequential Clock-to-Q
5.2
6.1
ns
tGO
Latch G-to-Q
5.2
6.1
ns
tRS
Flip-Flop (Latch) Reset-to-Q
5.2
6.1
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
2.4
2.8
ns
tRD2
FO=2 Routing Delay
3.4
4.0
ns
tRD3
FO=3 Routing Delay
4.2
4.9
ns
tRD4
FO=4 Routing Delay
5.1
6.0
ns
tRD8
FO=8 Routing Delay
9.2
10.8
ns
Logic Module Sequential Timing 3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.3
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
7.4
8.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.4
8.6
ns
tA
Flip-Flop Clock Input Period
16.4
22.1
ns
tINH
Input Buffer Latch Hold
2.5
ns
tINSU
Input Buffer Latch Setup
3.5
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
60
41
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
相關(guān)PDF資料
PDF描述
A14100A-1CQ256B FPGA, 1377 CLBS, 30000 GATES, 100 MHz, CQFP256
A1280A-1CQ172E FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172
A1460A-1CQ196E FPGA, 848 CLBS, 6000 GATES, 100 MHz, CQFP196
A1460A-1PG207E FPGA, 848 CLBS, 6000 GATES, 100 MHz, CPGA207
A1460A-CQ196E FPGA, 848 CLBS, 6000 GATES, 85 MHz, CQFP196
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1020B-CQ84E 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A1020B-CQ84M 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 84CQFP
A1020B-PG84B 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 1 2K GATES 547 CELLS 48MHZ 1.0UM 5V 84CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CPGA MIL
A1020B-PG84C 功能描述:IC FPGA 2K GATES 84-CPGA COM RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ACT™ 1 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門(mén)數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類(lèi)型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A1020B-PG84E 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*