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| 型號(hào)： | A1020B-CQ84C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84 |
| 封裝： | CERAMIC, CQFP-84 |
| 文件頁(yè)數(shù)： | 14/54頁(yè) |
| 文件大小： | 333K |
| 代理商： | A1020B-CQ84C |
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RadTolerant FPGAs
v3.1
1-17
RT1020, A1020B Timing Characteristics
Table 1-10 RT1020, A1020B Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
Std Speed
Parameter
Description
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
Single Module
3.6
ns
tPD2
Dual Module Macros
8.4
ns
tCO
Sequential Clock to Q
3.6
ns
tGO
Latch G to Q
3.6
ns
tRS
Flip-Flop (Latch) Reset to Q
3.6
ns
Logic Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
1.1
ns
tRD2
FO=2 Routing Delay
1.8
ns
tRD3
FO=3 Routing Delay
2.6
ns
tRD4
FO=4 Routing Delay
3.9
ns
tRD8
FO=8 Routing Delay
8.1
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Setup
6.9
ns
tHD
3
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
6.9
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
8.4
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
8.4
ns
tA
Flip-Flop Clock Input Period
17.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency (FO = 128)
55
MHz
Input Module Propagation Delays
tINYH
Pad to Y High
3.9
ns
tINYL
Pad to Y Low
3.9
ns
Input Module Predicted Routing Delays1, 3
tIRD1
FO=1 Routing Delay
1.1
ns
tIRD2
FO=2 Routing Delay
1.8
ns
tIRD3
FO=3 Routing Delay
2.6
ns
tIRD4
FO=4 Routing Delay
3.9
ns
tIRD8
FO=8 Routing Delay
8.1
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
2. Setup times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. Optimization techniques may further reduce delays by 0 to 4ns.
4. The hold time for the DFME1A macro may be greater than 0ns. Use the Designer software 3.0 (or later) Timer to check the hold
time for this macro.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1020B-CQ84E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1020B-CQ84M | 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 84CQFP |
| A1020B-PG84B | 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 1 2K GATES 547 CELLS 48MHZ 1.0UM 5V 84CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 2K GATES 84-CPGA MIL |
| A1020B-PG84C | 功能描述:IC FPGA 2K GATES 84-CPGA COM RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ACT™ 1 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A1020B-PG84E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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