參數(shù)資料
型號(hào)： 72V3684L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 5/36頁(yè)
文件大?。?/td> 418K
代理商： 72V3684L15PF
COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
13
Synchronized
Number of Words in FIFO Memory(1,2)
to CLKA
to CLKB
IDT72V3684(3)
IDT72V3694(3)
IDT72V36104(3)
EFA/ORA
AEA
AFB
FFB/IRB
000
L
H
1 to X2
H
L
H
(X2+1) to [16,384-(Y2+1)]
(X2+1) to [32,768-(Y2+1)]
(X2+1) to [65,536-(Y2+1)]
H
(16,384-Y2)to16,383
(32,768-Y2)to32,767
(65,536-Y2)to65,535
H
L
H
16,384
32,768
65,536
H
L
TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
TABLE 5 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
Number of Words in FIFO Memory(1,2)
to CLKB
to CLKA
IDT72V3684(3)
IDT72V3694(3)
IDT72V36104(3)
EFB/ORB
AEB
AFA
FFA/IRA
00
0
L
H
1 to X1
H
L
H
(X1+1) to [16,384-(Y1+1)]
(X1+1) to [32,768-(Y1+1)]
(X1+1) to [65,536-(Y1+1)]
H
(16,384-Y1)to16,383
(32,768-Y1)to32,767
(65,536-Y1)to65,535
H
L
H
16,384
32,768
65,536
H
L
LOW, and
FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when
CSA is LOW, W/RA is LOW,
ENA is HIGH, MBA is LOW, and
EFA/ORA is HIGH (see Table 2). FIFO
reads and writes on Port A are independent of any concurrent Port B
operation.
The Port B control signals are identical to those of Port A with the
exception that the Port B Write/Read select (
W/RB) is the inverse of the Port
A Write/Read select (W/
RA). The state of the Port B data (B0-B35) lines is
controlled by the Port B Chip Select (
CSB) and Port B Write/Read select (W/
RB). The B0-B35 lines are in the high-impedance state when either
CSB is
HIGH or
W/RB is LOW. The B0-B35 lines are active outputs when CSB is
LOW and
W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when
CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is
LOW, and
FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
byaLOW-to-HIGHtransitionofCLKBwhen
CSBisLOW,W/RBisHIGH,ENB
is HIGH, MBB is LOW, and
EFB/ORBisHIGH(seeTable3).FIFOreadsand
writes on Port B are independent of any concurrent Port A operation.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by
AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the
EFB and FFA functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by
AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRB functions are active during FWFT mode; the
EFA and FFB functions are active in IDT Standard mode.
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects
and Write/Read selects are only for enabling write and read operations and
are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of the
Read Clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO's memory array is clocked to the output
register only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select. Write and read timing diagrams for Port A
can be found in Figure 7 and 14. Relevant Port B write and read cycle timing
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