參數(shù)資料
型號(hào): 72V3684L15PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝: TQFP-128
文件頁數(shù): 21/36頁
文件大?。?/td> 418K
代理商: 72V3684L15PF
COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
28
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
CSA
ORA
W/
RA
MBA
ENA
A0-A35
CLKA
IRB
CLKB
CSB
4677 drw23
W/RB
B0-B35
MBB
ENB
12
tCLK
tCLKH
tCLKL
tENS2
tENH
tA
tSKEW1
tCLK
tCLKH
tCLKL
tWFF
tENS2
tENH
tDS
tDH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
FIFO2 FULL
LOW
HIGH
LOW
(1)
Write
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