參數(shù)資料
型號(hào)： 72V3684L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁數(shù)： 20/36頁
文件大?。?/td> 418K
代理商： 72V3684L15PF
COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
27
Figure 20.
FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for
FFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then
FFA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
CSB
ORB
W/RB
MBB
ENB
B0-B35
CLKB
IRA
CLKA
CSA
4677 drw21
W/
RA
A0-A35
MBA
ENA
12
tCLK
tCLKH
tCLKL
tENS2
tENH
tA
tSKEW1
tCLK
tCLKH
tCLKL
tWFF
tENS2
tDS
tENH
tDH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
tWFF
Write
CSB
EFB
MBB
ENB
B0-B35
CLKB
FFA
CLKA
CSA
4677 drw22
W/
RA
12
A0-A35
MBA
ENA
tCLK
tCLKH
tCLKL
tENS2
tENH
tA
tSKEW1
tCLK
tCLKH
tCLKL
tENS2
tDS
tENH
tDH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
W/RB
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
tWFF
Write
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