參數(shù)資料
型號: 72V3684L15PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝: TQFP-128
文件頁數(shù): 15/36頁
文件大?。?/td> 418K
代理商: 72V3684L15PF
COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
22
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
DATA READ FROM FIFO1
NO.
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A8-A0
B8-B0
HH
H
A
B
C
D
HH
L
A
B
C
D
1
A
2
B
3
C
4
D
1
D
2
C
3
B
4
A
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads.
NOTE:
1. Read From FIFO2.
EFB/ORB
MBB
CSB
W/RB
ENB
CLKB
HIGH
B0-B8
Read 5
Read 2
Read 3
Read 4
Read 3
Read 4
Previous Data
Read 2
No Operation
tDIS
tA
tENS2
tENH
tA
Read 1
(Standard Mode)
(FWFT Mode)
tEN
tMDV
tEN
OR
Read 1
4677 drw15
4677 drw16
CLKA
EFA/ORA
ENA
MBA
CSA
W/
RA
tCLK
tCLKH
tCLKL
tENS2
tA
tMDV
tEN
tA
tENS2
tENH
tENS2
tENH
W1
W2
W3
(1)
tENH
tDIS
No Operation
A0-A35
(FWFT Mode)
tEN
W2
(1)
tDIS
W1
Previous Data
A0-A35
(Standard Mode)
tMDV
tA
OR
tA
HIGH
(1)
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