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參數(shù)資料
| 型號： | 72V3684L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 418K |
| 代理商： | 72V3684L15PF |
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COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
2
PIN CONFIGURATION
TQFP (PK128-1, order code: PF)
TOP VIEW
W/
RA
CLKB
4677 drw02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/
FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
PRS2/RT2
Vcc
B35
B34
B33
B32
RTM
GND
B31
B30
B29
B28
B27
B26
Vcc
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
Vcc
B15
B14
B13
B12
GND
B11
B10
CSA
FFA
/IRA
EFA
/ORA
PRS1
R
T
1
Vcc
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
GND
FS1/
SEN
MRS2
MBB
MBF1
Vcc
AEB
AFB
EFB
/ORB
FFB
/IRB
GND
CSB
W
/RB
ENB
A9
A8
A7
A
6
G
N
D
A
5
A4
A3
Vcc
A2
A1
A0
GND
B0
B1
B2
B3
B
4
B
5
GND
B
6
Vcc
B7
B8
B
9
104
103
INDEX
SIZE
FS2
DESCRIPTION
The IDT72V3684/72V3694/72V36104 are designed to run off a 3.3V
supply for exceptionally low-power consumption. These devices are mono-
lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked)
FIFO memory which supports clock frequencies up to 100 MHz and has read
access times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36
dual-port SRAM FIFOs on board each chip buffer data in opposite directions.
FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats
with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers’ width matches the selected Port B bus width.
,
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72V3690L10PF | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V3690L10PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel |
| 72V3690L15PF | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V3690L15PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel |
| 72V3690L15PFI | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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