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參數(shù)資料
| 型號(hào)： | 7007L35PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 DUAL-PORT SRAM, 35 ns, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-80 |
| 文件頁(yè)數(shù)： | 9/21頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | 7007L35PF |
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17
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins
BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are
push-pull, not open drain outputs. On slaves the
BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either
BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.
2. There are eight semaphore flags written to via I/O5(I/O0 - I/O7) and read from all I/O0. These eight semaphores are addressed by A0 - A2.
3.
CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7007 provides two ports with separate control, address and
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7007hasanautomaticpowerdownfeaturecontrolled
by
CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (
CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
INTERRUPTS
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. The left port interrupt flag
(
INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as
CE = R/W = VIL per the Truth Table.
The left port clears the interrupt through access of address location 7FFE
when
CER = OER = VIL, R/W is a "don't care". Likewise, the right port
interruptflag(
INTR)isassertedwhentheleftportwritestomemorylocation
7FFF (HEX) and to clear the interrupt flag (
INTR),therightportmustread
thememorylocation7FFF. Themessage(8bits)at7FFEor7FFFisuser-
defined since it is an addressable SRAM location. If the interrupt function
isnotused,addresslocations7FFEand7FFFarenotusedasmailboxes,
butaspartoftherandomaccessmemory.RefertoTableIIIfortheinterrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of
the two accesses to proceed and signals the other side that the RAM is
Inputs
Outputs
Function
CEL
CER
AOL-A14L
AOR-A14R
BUSYL(1)
BUSYR(1)
XX
NO MATCH
H
Normal
H
X
MATCH
H
Normal
X
H
MATCH
H
Normal
L
MATCH
(2)
Write Inhibit
(3)
2940 tbl 17
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
2940 tbl 18
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參數(shù)描述 |
|---|---|
| 7007L35PF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 256K-Bit 32K x 8 35ns 80-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 256KBIT 32KX8 35NS 80TQFP - Tape and Reel |
| 7007L55J | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 7007L55J8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 7007L55PF | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 7007L55PF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 256K-Bit 32K x 8 55ns 80-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 256KBIT 32KX8 55NS 80TQFP - Tape and Reel |
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