參數(shù)資料
型號(hào): 7007L35PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 32K X 8 DUAL-PORT SRAM, 35 ns, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-80
文件頁數(shù): 21/21頁
文件大小: 168K
代理商: 7007L35PF
9
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
tRC
R/
W
CE
ADDR
tAA
OE
2940 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
CE
2940 drw 08
tPU
ICC
ISB
tPD
,
50%
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