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參數(shù)資料
| 型號(hào)： | 7007L35PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 DUAL-PORT SRAM, 35 ns, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-80 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 168K |
| 代理商： | 7007L35PF |
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
18
“busy”. The
BUSY pin can then be used to stall the access until the
operation on the other side is completed. If a write operation has been
attempted from the side that receives a
BUSYindication,thewritesignal
is gated internally to prevent the write from proceeding.
The use of
BUSYlogicisnotrequiredordesirableforallapplications.
In some cases it may be useful to logically OR the
BUSYoutputstogether
and use any
BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of
BUSYlogicis
not desirable, the
BUSYlogiccanbedisabledbyplacingthepartinslave
mode with the M/
Spin.OnceinslavemodetheBUSYpinoperatessolely
as a write inhibit input pin. Normal operation can be programmed by tying
the
BUSY pins HIGH. If desired, unintended write operations
can be prevented to a port by tying the
BUSY pin for that port LOW.
The
BUSY outputs on the IDT 7007 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the
BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
Semaphores
TheIDT7007isanextremelyfastDual-Port 16Kx8CMOSStaticRAM
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situations and may be used by the system program to avoid any conflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
an automatic power-down feature controlled by
CE,theDual-PortRAM
enable, and
SEM,thesemaphoreenable.TheCEand SEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where
CE and SEM are both HIGH.
Systems which can best use the IDT7007 contain multiple proces-
sors or controllers and are typically very high-speed systems which
are software controlled or software intensive. These systems can
benefit from a performance increase offered by the IDT7007 hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations. The IDT7007 does not use its semaphore flags to control
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speedsystems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform
anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7007 RAMs.
When expanding an IDT7007 RAM array in width while using
BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a
BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSYsignalasawriteinhibitsignal.ThusontheIDT7007RAMtheBUSY
pin is an output if the part is used as a master (M/
Spin=H),andtheBUSY
pin is an input if the part used as a slave (M/
S pin = L) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decision could result with one master indicating
BUSYononesideofthe
array and another master indicating
BUSYononeothersideofthearray.
This would inhibit the write operations from one port for part of a word and
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The
BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughfora
BUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/
Wsignal.Failuretoobservethistimingcan
result in a glitched internal write inhibit signal and corrupted data in the
slave.
2940 drw 19
MASTER
Dual Port
RAM
BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (R)
SLAVE
Dual Port
RAM
BUSY (R)
SLAVE
Dual Port
RAM
BUSY (R)
BUSY (L)
BUSY (R)
D
E
C
O
D
E
R
CE
BUSY (L)
,
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| 7007L35PF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 256K-Bit 32K x 8 35ns 80-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 256KBIT 32KX8 35NS 80TQFP - Tape and Reel |
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| 7007L55J8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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| 7007L55PF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 256K-Bit 32K x 8 55ns 80-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 5V 256KBIT 32KX8 55NS 80TQFP - Tape and Reel |
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