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| 型號(hào)： | 5962R0722402VYC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256 |
| 封裝： | QFP-256 |
| 文件頁(yè)數(shù)： | 92/155頁(yè) |
| 文件大?。?/td> | 4139K |
| 代理商： | 5962R0722402VYC |
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AT697F PRELIMINARY INFORMATION
41
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
The correctable error detection event is reported in the fail address register (FAILAR) and in the
fail status register (FAILSR). If unmasked, interrupt 1 (trap 0x11) is generated. The interrupt can
then be attached to a low priority interrupt handler that scrubs the failing memory location.
Uncorrectable error
If a double error is detected, this leads to an un-correctable error. An un-correctable error detec-
tion during a data access leads to a data access exception (trap 0x09). In case the double error
is detected during instruction fetch, it leads to an instruction access error (trap 0x01).
Figure 27.
Da
ta
B
u
s
Memory Configuration Reg.
MCFG3
CB[7:0]
EDAC
Fail Address Reg.
FAILAR
Fail Status Reg.
FAILSR
Add
re
ss
Bus
tr
ap
0x
01
tr
a
p
0x09
tr
a
p
0x11
EDAC overview
EDAC on 8-bit areas
The 8-bit mode applies to RAM and PROM while SDRAM always uses 32-bit accesses.
When a memory area is configured in 8-bit mode, the EDAC checkbit bus (CB[7:0]) is not used
but it is still possible to use EDAC protection.
The data bus mapped on D31:24 is always accessed in a 32-bit wide word basis (4bytes at a
time). The corresponding checkbits are located on top of the selected memory
bank according to the following operation:
The address A[27:2] of the 32-bit data word is inverted
The resulting address is then shifted twice right to become a byte address
The checkbit is written to the derived byte address while the data address chipselect is kept
active so that the current memory area is still active.
A word written as four bytes to addresses 0, 1, 2, 3 will have its checkbits at address
0x0FFFFFFF, addresses 4, 5, 6, 7 at 0x0FFFFFFE and so on.
Here is an example of checkbit addressing:
The data is written at address 0x00000004
Inversion of this address lids to 0xFFFFFFFB
Once shifted we have 0xFFFFFFFE
The checkbit is located at address 0xFFFFFFFE in the same memory bank as the data.
All the bits up to the maximum bank size will be inverted while the same chip-select is always
asserted.
This way all the bank size can be supported and no memory will be unused (except for a maxi-
mum of 4 Bytes in the gap between the data and checkbit area).
Here is an overview of the memory organization when EDAC is enbled on a 8-bit area.
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| 5962R0722601VZA | 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays |
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