參數(shù)資料
型號(hào): 5962R0722402VYC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝: QFP-256
文件頁數(shù): 121/155頁
文件大?。?/td> 4139K
代理商: 5962R0722402VYC
68
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
JTAG Interface
Overview
The AT697 implements a standard interface compliant with the IEEE 1149.1 JTAG specification.
This interface can be used for PCB testing using the JTAG boundary-scan capability.
The JTAG interface is accessed through five dedicated pins. In JTAG terminology, these pins
constitute the Test Access Port (TAP).
The following table summarizes the TAP pins and there function at JTAG level.
Table 24.
Pin
Name
Type
Description
TCK
Test Clock
Input
Used to clock serial data boundary into scan latches and control
sequence of the test state machine. TCK can be asynchronous
with CLK
TMS
Test Mode select
Input
Primary control signal for the state machine. Synchronous with
TCK. A sequence of values on TMS adjusts the current state of
the TAP.
TDI
Test Data Input
Input
Serial input data to the boundary scan latches. Synchronous
with TCK
TDO
Test Data Output
Output
Serial output data from the boundary scan latches.
Synchronous with TCK
TRST
Test Reset
Input
Resets the test state machine. can be asynchronous with TCK
TAP Pins
For more details, please refer to the ‘IEEE Standard Test Access Port and Boundary Scan’
specification.
Any AT697 based system will contain several JTAG compatible chips. These are connected
using the minimum (single TMS signal) configuration. This configuration contains three broad-
cast signals (TMS, TCK, and TRST,) which are fed from the JTAG master to all JTAG slaves in
parallel, and a serial path formed by a daisy-chain connection of the serial test data pins (TDI
and TDO) of all slaves.
The TAP supports a BYPASS instruction which places a minimum shift path (1 bit) between the
chip’s TDI and TDO pins. This allows efficient access to any single chip in the daisy-chain with-
out board-level multiplexing.
Figure 42. JTAG Serial connection using 1 TMS Signal
TDI
TDO
TMS TCK
TRST
TDI
TDO
TMS TCK
TRST
TDI
TDO
TMS TCK
TRST
TDI
TDO
TMS TCK
TRST
TDI
TMS
TCK
TRST
TDO
Part 1
Part 2
Part 3
Part n
相關(guān)PDF資料
PDF描述
5962R8958702VXA 5 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, CDSO16
5962R9215311VTA 32K X 8 STANDARD SRAM, 55 ns, CDFP36
5962R9215311VTX 32K X 8 STANDARD SRAM, 55 ns, CDFP36
5962G9215309VMX 32K X 8 STANDARD SRAM, 55 ns, CDIP28
5962F9215315VMC 32K X 8 STANDARD SRAM, 70 ns, CDIP28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962R0722601VZA 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays
5962R0722701VZA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
5962R0722902VXA 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓(最大值):307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
5962R0722961VXA 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓(最大值):307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
5962R0724902VPC 制造商:Intersil Corporation 功能描述: