參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 13/155頁
文件大?。?/td> 4139K
代理商： 5962R0722402VYC
11
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
This active low output is the chip-select signal for the memory mapped I/O area.
SDRAM Interface
SDCLK - SDRAM clock (output)
SDRAM clock provides the SDRAM interface clock reference.
SDCAS* - SDRAM column address strobe (output)
This active low signal provides a common CAS for all SDRAM devices.
SDCS*[1:0] - SDRAM chip select (output)
These active low outputs provide the chip select signals for the two SDRAM banks.
SDDQM[3:0] - SDRAM data mask (output)
These active low outputs provide the DQM signals for both SDRAM banks.
SDRAS*- SDRAM row address strobe (output)
This active low signal provides a common RAS for all SDRAM devices.
SDWE* - SDRAM write strobe (output)
This active low signal provides a common write strobe for all SDRAM devices.
System Signals
CLK - Processor clock (input)
The CLK input provides the main processor clock reference.
RESET* - Processor reset (input)
When asserted, this active low input will reset the processor and all on-chip peripherals.
WDOG* - Watchdog time-out (open-drain output)
This active low output is asserted when the watchdog expires.
BEXC* - Bus exception (input)
This active low input is sampled simultaneously with the data during accesses on the memory
bus. If asserted, a memory error will be generated.
ERROR* - Processor error (open-drain output)
This active low output is asserted when the processor has entered error state and is halted. This
happens when traps are disabled and a synchronous (un-maskable) trap occurs.
PIO[15:0] - Parallel I/O port (bi-directional)
These bi-directional signals can be used as inputs or outputs to control external devices.
BYPASS - PLL bypass (input)
When driven to VCC, this active high input set the PLL in bypass mode. The device is then
directly clocked by the external clock. When grounded, the device is clocked through the PLL.
SKEW[1:0] - Clock tree skew (input)
These input signals configurate the programmable skew on the triplicated clock trees.
LOCK - PLL lock (output)
This active high output is asserted when the PLL output (internal node) is locked at the fre-
quency corresponding to four times the input command.
DSU Signals
DSUACT - DSU active (output)
This active high output is asserted when the processor is in debug mode and controlled by the
DSU.
DSUBRE - DSU break enable (input)
相關(guān)PDF資料
PDF描述
5962R8958702VXA 5 V FIXED POSITIVE LDO REGULATOR, 1 V DROPOUT, CDSO16
5962R9215311VTA 32K X 8 STANDARD SRAM, 55 ns, CDFP36
5962R9215311VTX 32K X 8 STANDARD SRAM, 55 ns, CDFP36
5962G9215309VMX 32K X 8 STANDARD SRAM, 55 ns, CDIP28
5962F9215315VMC 32K X 8 STANDARD SRAM, 70 ns, CDIP28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962R0722601VZA 制造商:Texas Instruments 功能描述:D/A CONVERTER, 12-BIT - Trays
5962R0722701VZA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
5962R0722902VXA 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
5962R0722961VXA 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
5962R0724902VPC 制造商:Intersil Corporation 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*