參數(shù)資料
型號(hào)： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 142/155頁
文件大?。?/td> 4139K
代理商： 5962R0722402VYC
AT697F PRELIMINARY INFORMATION
87
7703D–AERO–12/09
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Note:
The prom bank size is coded in the same way as the ram bank size in MCFG2. The prom bank
size is used when an 8-bit prom is used with EDAC enabled - the last 25% of the prom bank is
used to store the EDAC checksums and cannot be used to store instructions or data.
During power-up, the prom width (bits [9:8]) are set with value on PIO[1:0] inputs. The prom
waitstates fields are set to 15 (maximum) and prom bank size is set to “0000”. External bus error
and bus ready are disabled. All other fields are undefined.
Table 46. Memory Configuration Register 2 - MCFG2
Address = 0x80000004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
sdr
ref
trp
trfc[2:0
]
sdr
c
as
sd
rbs[2:0]
sdrcls[1:0]
sdrcmd[1:0]
reserved
se
si
rambs[3:0]
re
s
e
rv
e
d
ra
mbrdy
rmw
ramwd
h[1:0]
ramwws[1:0]
ramrws[1:0]
r/w r/w
r/w
r/w r/w
r/w
r/w r/w r/w
r/w
0
1
111
1
000
10
00
xxxx
0
xxxx
x
xx
Bit Number
Mnemonic
Description
31
sdrref
SDRAM refresh.
If set, the SDRAM refresh will be enabled.
30
trp
SDRAM t
RP timing.
tRP will be equal to 2 or 3 system clocks (0/1).
29..27
trfc[2:0]
SDRAM t
RFC timing.
tRF will be equal to 3 + field-value system clocks.
26
sdrcas
SDRAM CAS delay.
Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOAD-COMMAND-REGISTER command must be
issued at the same time. Also sets RAS/CAS delay (tRCD).
25..23
sdrbs[2:0]
SDRAM banks size.
Defines the banks size for SDRAM chip selects:
“000” = 4 Mbyte,
“001” = 8 Mbyte,
“010” = 16 Mbyte,
...,
“111”=512 Mbyte.
22..21
sdrcls[1:0]
SDRAM column size.
“00” = 256 when sdrbs = “111”,
“01” = 512 when sdrbs = “111”,
“10” = 1024 when sdrbs = “111”,
“11” = 4096 when sdrbs = “111”,
= 2048 otherwise.
20..19
sdrcmd[1:0]
SDRAM command.
Writing a non-zero value will generate an SDRAM command:
“01” = PRECHARGE,
“10” = AUTO-REFRESH,
“11” = LOAD-COMMAND-REGISTER.
The field is reset after command has been executed.
14
se
SDRAM enable.
If set, the SDRAM controller will be enabled.
13
si
SRAM disable.
If set together with bit 14 (SDRAM enable), the static ram access will be disabled.
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