參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 73/155頁
文件大?。?/td> 4139K
代理商： 5962R0722402VYC
24
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Non Maskable
Interrupt (NMI)
The AT697F handles interrupt 15 (trap type TT = 0x1F). This interrupt can not be masked by the inte-
ger unit of the processor. It shall be used with care as the NMI of the processor.
I/O interrupts
As an alternate function of the general purpose interface, the AT697F allows to input interrupt
from external devices. Up to eight external interrupts can be programmed at the same time. The
external interrupts are assigned to interrupt 4, 5, 6, 7,10, 12, 13 and 15.
Two registers are defined for configuration of the IO interrupts :
IOIT1 register is used for control of IO interrupt 0, 1, 2 and 3
IOIT2 register is used for control of IO interrupt 4, 5, 6 and 7
Each I/O interrupt is controlled through four fields in one of the above register (IOITx) : ENx,
LEx, PLx and ISELx.
An I/O interrupt is enabled setting logical one to IOITx ENx . Setting this bit logical zero dis-
ables the interrupt. The IOITx ISELx defines which port of the general purpose interface should
generate I/O interrupt x. The port can be selected from within PIO[15:0] and D[15:0]*.
Each I/O interrupt can have its trigger mode and its polarity individually configured. When bit
IOITx LEx is set logical one, the corresponding I/O interrupt is edge triggered. If the polarity bit
IOITx PLx is driven logical one the interrupt triggers when a rising edge is applied on the pin. If
the polarity bit is driven logical zero the interrupt triggers when a falling edge is applied on the
pin.
When the bit IOITx LEx is set logical zero, the corresponding I/O interrupt is level sensitive. If
the polarity bit IOITx PLx is driven logical one the interrupt triggers when a high level is applied
on the pin. If the polarity bit is driven logical zero the interrupt triggers when a low level is applied
on the pin.
The following table summarizes the I/O interrupt configurations.
Table 10.
LEx
PLx
Trigger
0
low level
0
1
high level
1
0
falling edge
1
rising edge
I/O Interrupt Configuration
2
0x12
UART 2
1
0x11
Internal bus error
Interrupt
TT (Trap Type)
Source
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