參數(shù)資料
型號： 5962R0722402VYC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封裝： QFP-256
文件頁數(shù)： 150/155頁
文件大小： 4139K
代理商： 5962R0722402VYC
94
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
R
Y
IN
FOR
M
AT
IO
N
Caches Register
Table 57. Cache Control Register - CCR
Address = 0x80000014
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ds
fd
fi
cpc[1:0]
cpte[1
:0]
ib
ip
dp
ite[1:0]
ide[1:
0]
d
te[1:0]
dde
[1:0]
df
if
dcs[1:0]
ics[1:0]
r
r/w r/w r/w
r
r/w
r
r/w
r/w r/w
r/w
11110111
0
10
xx
0
x
00
x
00
Bit Number
Mnemonic
Description
23
ds
Data cache snoop enable
If set, will enable data cache snooping.
22
fd
Flush data cache
If set, will flush the data cache. Always reads as zero.
21
fi
Flush Instruction cache
If set, will flush the instruction cache. Always reads as zero.
20..19
cpc[1:0]
Cache parity bits
Indicates how many parity bits are used to protect the caches
“00” = none,
“01” = 1 parity bits,
“10” = 2 parity bits,
“11” = not used
18..17
cpte[1:0]
Cache parity test bits
These bits are XOR’ed to the data and tag parity bits during diagnostic writes.
16
ib
Instruction burst fetch
This bit enables burst fill during instruction fetch.
15
ip
Instruction cache flush pending
This bit is set when an instruction cache flush operation is in progress.
14
dp
Data cache flush pending
This bit is set when an data cache flush operation is in progress.
13..12
ite[1:0]
Instruction cache tag error counter
This filed is incremented every time an instruction cache tag parity error is detected.
11.10
ide[1:0]
Instruction cache data error counter
This field is incremented each time an instruction cache data sub-block parity error is detected.
9..8
dte[1:0]
Data cache tag error counter
This filed is incremented every time a data cache tag parity error is detected.
7..6
dde[1:0]
Data cache data error counter
This field is incremented each time an instruction cache data sub-block parity error is detected
5
df
Data Cache Freeze on Interrupt
If set, the data cache will automatically be frozen when an asynchronous interrupt is taken.
4
if
Instruction Cache Freeze on Interrupt
If set, the instruction cache will automatically be frozen when an asynchronous interrupt is taken.
3..2
dcs[1:0]
Data Cache state
Define the current data cache according to the following :
“X0” = disabled
“01” = frozen
“11” = enabled
Set to “00” at reset.
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