
322
μPD780948, μPD78F0948, μPD780949, μPD78F0949
18.16
Interrupt Information
18.16.1 Interrupt vectors
The DCAN peripheral supports four interrupt sources as shown in the following table.
Table 18-28: Interrupt Sources
18.16.2 Transmit interrupt
The transmit interrupt is generated when all following conditions are fulfilled:
The transmit interrupt 0 is generated when TXRQ0 bit is cleared.
The transmit interrupt 1 is generated when TXRQ1 bit is cleared.
Clearing of this bits mean that the buffer gets free for writing a new message into it. The clear can occur
due to a successful transmission or due to an abort of a transmission and can only cleared by the DCAN.
18.16.3 Receive interrupt
The receive interrupt is generated when all following conditions are fulfilled:
CAN protocol port marks received frame valid
Memory access engine finds a message buffer with a identifier/mask combination that fits to the
receive frame
Memory access engine successfully stored data in the message buffer
The message buffer is marked for interrupt generation with ENI bit set
The Memory access engine compare and storage function can delay the interrupt up to the 7th bit of the
next frame.
18.16.4 Error interrupt
The error interrupt is generated when all following conditions are fulfilled:
Transmission error counter (BOFF) changes it state.
Transmission error counter status (TECS) changes it state.
Reception error status (RECS) changes it state.
Overrun during RAM access (OVER) changes it state.
The wake-up condition (WAKE) occurs.
The internal WAKE conditions sets the interrupt high. The interrupt is kept high until the DCAN has got
enough clock cycles to safely restart all internal activities. This may need several bit periods of the CAN
bus.
Function
Source
Interrupt Flag
Error
Error counter
Overrun error
Wake up
Received frame is valid
TXRQ0 is cleared
TXRQ1 is cleared
CEIF
Receive
Transmit buffer 0
Transmit buffer 1
CRIF
CTIF0
CTIF1