21
μPD780948, μPD78F0948, μPD780949, μPD78F0949
Figure No.
Title
Page
19-1
19-2
19-3
19-4
19-5
LCD Controller/Driver Block Diagram ..............................................................................
LCD Clock Select Circuit Block Diagram ........................................................................
LCD Display Mode Register (LCDM) Format ...................................................................
LCD Display Control Register (LCDC) Format .................................................................
Relationship between LCD Display Data Memory Contents and Segment/Common
Outputs L........................................................................................................................
Common Signal Waveform ..............................................................................................
Common Signal and Segment Signal Voltages and Phases ............................................
Example of Connection of LCD Drive Power Supply........................................................
4-Time-Division LCD Display Pattern and Electrode Connections....................................
4-Time-Division LCD Panel Connection Example ............................................................
4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ...............................
LCD Timer Control Register (LCDTM) Format..................................................................
332
333
334
335
337
339
339
341
342
343
344
345
19-6
19-7
19-8
19-9
19-10
19-11
19-12
20-1
20-2
20-3
20-4
20-5
20-6
20-7
Sound Generator Block Diagram.....................................................................................
Concept of Each Signal ..................................................................................................
Sound Generator Control Register (SGCR) Format .........................................................
Sound Generator Buzzer Control Register (SGBR) Format .............................................
Sound Generator Amplitude Register (SGAM) Format ....................................................
Sound Generator Output Operation Timing......................................................................
Sound Generator Output Operation Timing......................................................................
347
348
350
352
353
354
354
21-1
21-2
21-3
21-4
21-5
Basic Configuration of Interrupt Function (2/2) ................................................................
Interrupt Request Flag Register Format ..........................................................................
Interrupt Mask Flag Register Format...............................................................................
Priority Specify Flag Register Format .............................................................................
Formats of External Interrupt Rising Edge Enable Register and External Interrupt
Falling Edge Enable Register ..........................................................................................
Program Status Word Format..........................................................................................
Flowchart from Non-Maskable Interrupt Generation to Acknowledge...............................
Non-Maskable Interrupt Request Acknowledge Timing ....................................................
Non-Maskable Interrupt Request Acknowledge Operation ...............................................
Interrupt Request Acknowledge Processing Algorithm ....................................................
Interrupt Request Acknowledge Timing (Minimum Time) .................................................
Interrupt Request Acknowledge Timing (Maximum Time) ................................................
Multiple Interrupt Example (2/2) ......................................................................................
Interrupt Request Hold ....................................................................................................
358
361
362
363
364
365
367
367
368
370
371
371
373
375
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
21-14
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
Memory Map when Using External Device Expansion Function (2/2) ..............................
Memory Expansion Mode Register Format .....................................................................
Memory Expansion Wait Register Format .......................................................................
Memory Size Switching Register Format ........................................................................
Instruction Fetch from External Memory .........................................................................
External Memory Read Timing ........................................................................................
External Memory Write Timing ........................................................................................
External Memory Read Modify Write Timing....................................................................
Connection Example of μPD780949 and Memory ...........................................................
378
380
381
382
384
385
386
387
388