
304
μPD780948, μPD78F0948, μPD780949, μPD78F0949
BOFF
Bus Off Flag
0
Transmission error counter
≤
255
Transmission error counter = 255
1
RECS
Reception error counter status
0
Reception error counter <
96
Reception error counter
≥
96 / Warning level for error passive reached
1
TECS
Transmission error counter status
0
Transmission error counter <
96
Transmission error counter
≥
96 / Warning level for error passive
reached
It changes when the contents of the reception error counter changes.
1
INITSTATE
INIT accepted
0
CAN is in normal operation
1
CAN is stopped and ready to accept new configuration data
VALID
Valid protocol activity detected
0
No valid message detected by the CAN protocol
1
Error free message reception from CAN bus
18.13.2 CAN error status register
These register sets the CAN error status of the transmission and reception.
CANES has to be set with an 8-bit memory manipulation instruction.
RESET input sets CANC to 00H.
Figure 18-38: CAN Error Status Register
It changes when the contents of the transmission error counter has changed.
It changes when the contents of the reception error counter changes.
It changes with a delay to the INIT bit in CANC. The delay is dependent on running bus activity and
the time to set all internal activities to inactive state. Time can be several bit times long.
This bit shows valid protocol activities independent from the message definitions.
Whenever a frame is successsfully received by the protocol, it is irrespective of the identifier and mask
settings of the DCAN. It is set at the end of the frame part.
Cautions:
1. The VALID bit is cleared if CPU writes “1” to it, or when the INIT-bit in CANC is set.
2. Writing a 0 to the valid bit has no influence.
Symbol
7
6
5
4
3
2
1
0
Address
After Reset
R/W
CANES
BOFF
RECS
TECS
0
INITSTATE
VALID
WAKE
OVER
FFB4H
00h
R/W
BOFF, RECS, TECS and INITSTATE are read only bits.