258
μPD780948, μPD78F0948, μPD780949, μPD78F0949
(d) Reception
The receive operation is enabled when “1” is set to bit 6 (RXE0) of the asynchronous serial interface mode
register (ASIM0), and input data via RxD pin is sampled.
The serial clock specified by ASIM0 is used when sampling the RxD pin.
When the RxD pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling
is output if half of the specified baud rate time has elapsed. If the sampling of the RxD0 pin input of this
start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized
and starts counting and data sampling begins. After the start bit is recognized, the character data, parity
bit, and one-bit stop bit are detected, at which point reception of one data frame is completed.
Once the reception of one data frame is completed, the receive data in the shift register is transferred
to the receive buffer register (RXB0) and a receive completion interrupt (INTSR) occurs.
Even if an error has occurred, the receive data in which the error occurred is still transferred to RXB0
and INTSR occurs (see Figure 17-9).
If the RXE0 bit is reset (to “0”) during a receive operation, the receive operation is stopped immediately.
At this time, neither the contents of RXB0 and ASIS0 do not change, nor does INTSR or INTSER occur.
Figure 17-12 shows the timing of the asynchronous serial interface receive completion interrupt.
Figure 17-12: Timing of Asynchronous Serial Interface Receive Completion Interrupt
Caution:
Be sure to read the contents of the receive buffer register (RXB0) even when a receive
error has occurred. Overrun errors will occur during the next data receive operations
and the receive error status will remain until the contents of RXB0 are read.
RxD (input)
D0
D1
D2
D6
D7
Parity
STOP
START
INTSR