22
μPD780948, μPD78F0948, μPD780949, μPD78F0949
Figure No.
Title
Page
23-1
23-2
23-3
23-4
23-5
Oscillation Stabilization Time Select Register Format .....................................................
HALT Mode Clear upon Interrupt Generation ...................................................................
HALT Mode Release by RESET Input ............................................................................
STOP Mode Release by Interrupt Generation..................................................................
Release by STOP Mode RESET Input............................................................................
391
393
394
396
397
24-1
24-2
24-3
24-4
Block Diagram of Reset Function ...................................................................................
Timing of Reset Input by RESET Input ...........................................................................
Timing of Reset due to Watchdog Timer Overflow ...........................................................
Timing of Reset Input in STOP Mode by RESET Input ...................................................
399
400
400
400
25-1
25-2
25-3
25-4
25-5
25-6
Memory Size Switching Register Format ........................................................................
Internal Expansion RAM Size Switching Register Format ...............................................
Transmission Method Selection Format ..........................................................................
Connection of Flashpro Using 3-Wire Serial I/O Method..................................................
Flashpro Connection Using UART Method ......................................................................
Flashpro Connection Using Pseudo 3-wire Serial I/O ......................................................
406
407
408
409
410
410
A-1
Development Tool Configuration ......................................................................................
428