Z8 Microcontrollers
Interrupts
ZiLOG
UM001600-Z8X0599
7-9
7.5 IRQ SOFTWARE INTERRUPT GENERATION
IRQ can be used to generate software interrupts by spec-
ifying IRQ as the destination of any instruction referencing
the Z8 Standard Register File. These Software Interrupts
(SWI) are controlled in the same manner as hardware gen-
erated requests (in other words, the IPR and the IMR con-
trol the priority and enabling of each SWI level).
To generate a SWI, the desired request bit in the IRQ is set
as follows:
where the immediate data, NUMBER, has a 1 in the bit po-
sition corresponding to the level of the SWI desired. For
example, if an SWI is desired on IRQ5, NUMBER would
have a 1 in bit 5:
With this instruction, if the interrupt system is globally en-
abled, IRQ5 is enabled, and there are no higher priority
pending requests, control is transferred to the service rou-
tine pointed to by the IRQ5 vector.
7.6 VECTORED PROCESSING
Each Z8 interrupt level has its own vector. When an inter-
rupt occurs, control passes to the service routine pointed
to by the interrupt’s vector location in program memory.
The sequence of events for vectored interrupts is as fol-
lows:
PUSH PC Low Byte on Stack
PUSH PC High Byte on Stack
PUSH FLAGS on Stack
Fetch High Byte of Vector
Fetch Low Byte of Vector
Branch to Service Routine specified by Vector
Figures 7-11 and 7-12 show the vectored interrupt opera-
tion.
ORIRQ,
#NUMBER
OR
IRQ, #00100000B
Figure 7-11. Effects of an Interrupt on the STACK
SP
Top of Stack
PC LOW Byte
PC HIGH Byte
FLAGS
SP and Stack after an interrupt
SP
SP and Stack before an interrupt