UM001600-Z8X0599
6-1
U
SER
’
S
M
ANUAL
C
HAPTER
6
C
OUNTER
/T
IMERS
6.1 INTRODUCTION
The Z8 MCU
provides up to two 8-bit counter/timers, T0
and T1, each driven by its own 6-bit prescaler, PRE0 and
PRE1 (Figure 6-1). Both counter/timers are independent of
the processor instruction sequence, that relieves software
from time-critical operations such as interval timing or
event counting. Some MCUs offer clock scaling using the
SMR register. See the device product specification for
clock available options. The following description is typical.
Each counter/timer operates in either Single-Pass or Con-
tinuous mode. At the end-of-count, counting either stops or
the initial value is reloaded and counting continues. Under
software control, new values are loaded immediately or
when the end-of-count is reached. Software also controls
the counting mode, how a counter/timer is started or
stopped, and its use of I/O lines. Both the counter and
prescaler registers can be altered while the counter/timer
is running.
Figure 6-1. Counter/Timer Block Diagram
÷
2
OSC
D1 (SMR)
÷
16
D0 (SMR)
Clock
Logic
÷
4
Internal
Clock
External Clock
Internal Clock
Gated Clock
Triggered Clock
T
IN
P31
÷
4
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Read
Write
Write
Read
Write
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
÷
2
Internal Data Bus
Internal Data Bus
T
P36
IRQ
4
IRQ
5