Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001600-Z8X0599
12-81
XOR
LOGICAL EXCLUSIVE OR
XOR
Logical Exclusive OR
XOR dst, src
Instruction Format:
Operation:
dst <— dst XOR src
The source operand is logically EXCLUSIVE ORed with the destination operand. The XOR operation
results in a 1 being stored in the destination operand whenever the corresponding bits in the two
operands are different, otherwise a 0 is stored. The contents of the source operand are not affected.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or
destination Working Register operand is specified by adding 1110B (EH) to the high nibble of the
operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used
as the destination operand in the Op Code.
Example:
If Working Register R1 contains 34H (00111000B) and Working Register R14 contains 4DH
(10001101B), the statement:
XOR R1, R14
Op Code: B2 1E
leaves the value BDH (10111101B) in Working Register R1. The Z, and V Flags are cleared, and the S
Flag is set.
dst
src
OPC
OPC
OPC
src
dst
dst
src
6
6
Cycles
OPC
(Hex)
Address
dst
Mode
src
B2
B3
r
r
r
Ir
10
10
B4
B5
R
R
R
IR
10
10
B6
B7
R
IR
IM
IM
Flags:
C:
Z:
S:
V:
D:
H:
Unaffected
Set if the result is zero; cleared otherwise.
Set if the result of bit 7 is set; cleared otherwise.
Always reset to 0
Unaffected
Unaffected
E
src
E
dst
or