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XRT94L31
108
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
NOTE: The value for t4, t5, t5A and t5B can be found in
1.3.1.2
The Receive STS-3/STM-1 Telecom Bus Interface Timing
In the Receive STS-3/STM-1 Telecom Bus Interface, all of the signals (which are input via this Bus Interface)
are sampled upon the rising edge of RxD_CLK (19.44MHz clock signal).
Figure 14 presents an illustration of the waveforms and the timing parameters (t2 and t3) of the signals that will
be received by the Receive STS-3/STM-1 Telecom Bus Interface.
FIGURE 13. AN ILLUSTRATION OF THE TIMING RELATIONSHIPS BETWEEN THE TXSBFP INPUT PIN AND THE
TXA_CLK OUTPUT PIN WITHIN THE TRANSMIT STS-3/STM-1 TELECOM BUS INTERFACE
TABLE 8: TIMING INFORMATION FOR THE TRANSMIT STS-3/STM-1 TELECOM BUS INTERFACE
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t1
Rising edge of TxA_CLK to updates in TxA_D[7:0], TxA_PL,
TxA_C1J1 and TxA_DP
1.7ns
7.7ns
t4
TxSBFP Set-up time to rising edge of TxA_CLK
8.5ns
t5
TxA_CLK rising edge to TxSBFP Hold time
0ns
t5A
TxSBFP Set-up time to rising edge of REFCLK
5ns
t5B
Rising edge of REFCLK to TxSBFP Hold Time
0ns
t4
TxA_D[7:0]
TxSBFP
Data
A1
Data
TxA_CLK
t5
REFCLK
t5A
t5B