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參數(shù)資料
| 型號(hào)： | XRD98L63ZEVAL |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 41/41頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XRD98L63 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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9
Rev.1.01
XRD98L63
Table 1. Serial Interface Register Address Map & default values
Address bits
Data bits
Reg. Name A5 A4 A3 A2 A1 A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PGA00
0
PGA00[9]
0
PGA00[0]
0
Offset
0
1
OB[7]
1
0
OB[0]
0
PGA01
0
1
0
PGA01[8]
0
PGA01[0]
0
PGA10
0
1
PGA10[8]
0
PGA10[0]
0
PGA11
0
1
0
PGA11[8]
0
PGA11[0]
0
OB Even
Gain
0
1
0
1
OBE[8]
0
OBE[0]
0
OB Odd
Gain
0
1
0
OBO[8]
0
OBO[0]
0
Even Line
0
1
PRE[1]
0
PRE[0]
1
ELP4[1]
0
ELP4[0]
0
ELP3[1]
0
ELP3[0]
0
ELP2[1]
1
ELP2[0]
1
ELP1[1]
1
ELP1[0]
0
Odd Line
0
1
0
PRO[1]
0
PRO[0]
1
OLP4[1]
0
OLP4[0]
0
OLP3[1]
0
OLP3[0]
0
OLP2[1]
0
OLP2[0]
0
OLP1[1]
0
OLP1[0]
1
Calibration
0
1
0
1
OBdel[1]
0
OBdel[0]
0
Avg[1]
1
Avg[0]
0
DNS[1]
0
DNS[0]
1
Mode
0
Hold
0
ManCal
0
Wait A
0
1
0
1
0
WL[11]
0
WL[2]
0
Wait B
0
1
0
1
WL[1]
0
WL[0]
1
OB Lines
0
1
0
OBL[7]
0
1
OBL[0]
0
CDAC Even 0
0
1
0
1
CDE[8]
0
CDE[0]
0
CDAC Odd
0
1
0
CDO[8]
0
CDO[0]
0
FDAC Even 0
0
1
FDE[9]
0
FDE[0]
0
FDAC Odd
0
1
0
FDO[9]
0
FDO[0]
0
Control
0
1
0
1
ADCpd
0
AFEpd
0
CHIPpd
0
OE
1
MultGain
0
MGsel[1]
0
MGsel[0]
0
MGstart
0
MinClip
1
OneV
0
Test
0
1
0
1
0
nofs2
0
*Reserved
0
*Reserved
0
*Reserved
1
*Reserved
0
ADCin
0
NoCDS
0
*Reserved
0
*Reserved
0
Polarity
0
1
0
1
PBLKpol
0
EOSpol
1
SBLKpol
0
SPIXpol
0
CALpol
0
CLAMPpol
0
FSYNCpol
0
ADCpol
0
Clock
0
1
0
1
0
ADCLKsel
0
CLAMPopt
0
CALonly
0
SPIXopt
0
RSTreject
0
DOclamp
1
SBLKdly
0
1
0
1
0
1
SBdly[5]
0
SBdly[0]
0
SPIXdly
0
1
0
1
0
SPdly[8]
0
SPdly[0]
0
ADCdly
0
1
0
1
ADCdly[7]
0
ADCdly[0]
0
ReadBack
1
0
RBenable
0
RBreg[8]
0
RBreg[0]
0
Reset
1
Reset
0
Note: Shaded cells represent unused bits.
* Reserved Test register bits. Used for factory test only. Please do not modify.
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