Rev.1.01 XRD98L63 PIXEL RATE CLOCKS SBLK, SPIX & ADCLK Note: The timing descriptions in this section are correct for the default conditi" />
參數(shù)資料
型號(hào)： XRD98L63ZEVAL
廠商： Exar Corporation
文件頁(yè)數(shù)： 16/41頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XRD98L63
標(biāo)準(zhǔn)包裝： 1
系列： *
23
Rev.1.01
XRD98L63
PIXEL RATE CLOCKS SBLK, SPIX & ADCLK
Note:
The timing descriptions in this section are
correct for the default conditions:
All Polarity bits = 0,
RSTreject = 0 (switch always ON),
SPIXopt = 0
Sampling of the pixel black level is controlled by the
SBLK pulse. When SBLK is low, t
PW1, the internal
sample black switches in the CDS are ON, sampling the
pixel black level on the internal black sample capaci-
tors.
Sampling of the pixel video level is controlled by the
SPIX pulse. When SPIX is low, t
PW2, the video signal
propagates through the CDS amp and is sampled on the
internal video sampling capacitors. When SPIX goes
high, PGA1 gains up the signal from the video sample
capacitors.
Figure 16. Detailed Pixel Rate Clock Timing for Default Register Settings
PGA2 and the ADC form an analog pipeline controlled
by ADCLK. When ADCLK is high, PGA2 is sampling the
output of PGA1. When ADCLK goes low, PGA2 gains
up the sampled signal and the first stage of the ADC
samples the output of PGA2. ADCLK should be as
close as possible to 50% duty cycle.
If your timing generator does not provide a clock signal
suitable for ADCLK, there is an option to generate
ADCLK internally. Write a "1" to the "ADCLKsel" bit in
the Clock register. This will generate an internal
ADCLK based on the SBLK and SPIX clock signals.
We recommend that the ADCLK pin be tied to ground
when the ADCLKsel option is used.
SBLK
SPIX
CCD
Signal
t
PIX
ADCLK
t
BK
t
VD
t
DL
t
PW1
t
PW2
Black Sample Point
Video Sample Point
DB[11:0]
Data N-8
Data N-7
(pixel "N")
(pixel "N+1")
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