Rev.1.01 XRD98L63 Reset Reject In the default state, the reset reject switches ( φ3) are always ON; they are not clocked. The reset pulse of" />
參數(shù)資料
型號： XRD98L63ZEVAL
廠商： Exar Corporation
文件頁數(shù)： 18/41頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XRD98L63
標準包裝： 1
系列： *
25
Rev.1.01
XRD98L63
Reset Reject
In the default state, the reset reject switches (
φ3) are
always ON; they are not clocked. The reset pulse of
each pixel is transmitted to the first stage of the PGA.
Depending on the PGA gain and the actual voltage
level of the reset pulse, this could cause the first stage
of the PGA to rail. During the Black Level sampling, the
PGA should have enough time to recuperate, but as a
precaution, we have included the Reset Reject option.
When RSTreject = 1, the reset reject switches are
turned OFF at the end of the SPIX pulse and turned ON
again at the start of the SBLK pulse. This will effec-
tively reject the reset pulse and prevent it from railing
the PGA.
Figure 19. Pixel Rate Clock Timing with RSTreject=1
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
φ3
Reset Reject
Switches Turn OFF
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