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參數(shù)資料
| 型號： | XRD98L59AIGTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 6/37頁 |
| 文件大小： | 0K |
| 描述： | IC CCD DIGITIZER 10BIT 28TSSOP |
| 產(chǎn)品變化通告： | Obsolescence Notification 15/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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XRD98L59
14
Rev. 2.00
RSTREJ reduces CCD reset noise by disconnecting the
input of the XRD98L59 from the CCD during the CCD
reset pulse. RSTREJ is an internally generated signal.
RSTREJ disconnects the input after the SPIX and before
the SBLK sampling events to reject CCD reset noise.
The RSTREJ switch is always closed (the input is always
connected) if D6=0 in the clock register (address 0011)
of the serial port.
For the timing example shown in Figure 6, SBLK high
samples the pixel black level. The actual hold point of
the pixel black level occurs after a delay of tBK. tBK is
the aperture delay of the SBLK timing signal.
The polarities of the SBLK and SPIX signals are indepen-
dently programmable via the serial port.
For the timing example shown in Figure 6, SPIX high
samples the pixel video level. The actual hold point of
the pixel video level occurs after a delay of tVD. tVD is
the aperture delay of the SPIX timing signal. The
polarity of the SPIX signal is serial port programmable.
The function of the CDS block, shown in Figure 7, is to
sense the voltage difference between the black level and
video level for each pixel. The CDS and PGA are fully
differential to reject common mode noise. The PGA
output is converted to a single ended signal, and then fed
to the ADC.
REF
IN (CDS non-inverting input) should be connected,
via a capacitor, to the CCD “Common” voltage. This is
typically CCD ground.
CCD
IN (CDS inverting input)
should be connected, via a capacitor, to the CCD output
signal. The external coupling capacitors on CCD
IN and
REF
IN should be of equal values to minimize gain errors
(typically 0.01
f +/-10%).
Figure 7. Block Diagram of the CDS, Reset Phase: RSTREJ Switch is Open
+
PGA1
-
Vbias1 ~0.8
External
Coupling
Capacitors
VBIAS2
CLAMP
φ1
Gain
Register
to ADC
C
D
GND
Vout
C1
C2
C3
+
PGA2
-
+
BUF
-
C4
φ2
RSTREJ
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L59AIGTR-F | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| XRD98L61 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61_01 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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